/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh */ #include <linux/bits.h> #include <linux/can/dev.h> #include <linux/kernel.h> #include <linux/netdevice.h> #include <linux/units.h> #define ACC_TS_FREQ_80MHZ … #define ACC_I2C_ADDON_DETECT_DELAY_MS … /* esdACC Overview Module */ #define ACC_OV_OF_PROBE … #define ACC_OV_OF_VERSION … #define ACC_OV_OF_INFO … #define ACC_OV_OF_CANCORE_FREQ … #define ACC_OV_OF_TS_FREQ_LO … #define ACC_OV_OF_TS_FREQ_HI … #define ACC_OV_OF_IRQ_STATUS_CORES … #define ACC_OV_OF_TS_CURR_LO … #define ACC_OV_OF_TS_CURR_HI … #define ACC_OV_OF_IRQ_STATUS … #define ACC_OV_OF_MODE … #define ACC_OV_OF_BM_IRQ_COUNTER … #define ACC_OV_OF_BM_IRQ_MASK … #define ACC_OV_OF_MSI_DATA … #define ACC_OV_OF_MSI_ADDRESSOFFSET … /* Feature flags are contained in the upper 16 bit of the version * register at ACC_OV_OF_VERSION but only used with these masks after * extraction into an extra variable => (xx - 16). */ #define ACC_OV_REG_FEAT_MASK_CANFD … #define ACC_OV_REG_FEAT_MASK_NEW_PSC … #define ACC_OV_REG_FEAT_MASK_DAR … #define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE … #define ACC_OV_REG_MODE_MASK_BM_ENABLE … #define ACC_OV_REG_MODE_MASK_MODE_LED … #define ACC_OV_REG_MODE_MASK_TIMER_ENABLE … #define ACC_OV_REG_MODE_MASK_TIMER_ONE_SHOT … #define ACC_OV_REG_MODE_MASK_TIMER_ABSOLUTE … #define ACC_OV_REG_MODE_MASK_TIMER … #define ACC_OV_REG_MODE_MASK_TS_SRC … #define ACC_OV_REG_MODE_MASK_I2C_ENABLE … #define ACC_OV_REG_MODE_MASK_MSI_ENABLE … #define ACC_OV_REG_MODE_MASK_NEW_PSC_ENABLE … #define ACC_OV_REG_MODE_MASK_FPGA_RESET … /* esdACC CAN Core Module */ #define ACC_CORE_OF_CTRL … #define ACC_CORE_OF_STATUS_IRQ … #define ACC_CORE_OF_BRP … #define ACC_CORE_OF_BTR … #define ACC_CORE_OF_FBTR … #define ACC_CORE_OF_STATUS … #define ACC_CORE_OF_TXFIFO_CONFIG … #define ACC_CORE_OF_TXFIFO_STATUS … #define ACC_CORE_OF_TX_STATUS_IRQ … #define ACC_CORE_OF_TX_ABORT_MASK … #define ACC_CORE_OF_BM_IRQ_COUNTER … #define ACC_CORE_OF_TXFIFO_ID … #define ACC_CORE_OF_TXFIFO_DLC … #define ACC_CORE_OF_TXFIFO_DATA_0 … #define ACC_CORE_OF_TXFIFO_DATA_1 … /* CTRL register layout */ #define ACC_REG_CTRL_MASK_RESETMODE … #define ACC_REG_CTRL_MASK_LOM … #define ACC_REG_CTRL_MASK_STM … #define ACC_REG_CTRL_MASK_TRANSEN … #define ACC_REG_CTRL_MASK_TS … #define ACC_REG_CTRL_MASK_SCHEDULE … #define ACC_REG_CTRL_MASK_IE_RXTX … #define ACC_REG_CTRL_MASK_IE_TXERROR … #define ACC_REG_CTRL_MASK_IE_ERRWARN … #define ACC_REG_CTRL_MASK_IE_OVERRUN … #define ACC_REG_CTRL_MASK_IE_TSI … #define ACC_REG_CTRL_MASK_IE_ERRPASS … #define ACC_REG_CTRL_MASK_IE_ALI … #define ACC_REG_CTRL_MASK_IE_BUSERR … /* BRP and BTR register layout for CAN-Classic version */ #define ACC_REG_BRP_CL_MASK_BRP … #define ACC_REG_BTR_CL_MASK_TSEG1 … #define ACC_REG_BTR_CL_MASK_TSEG2 … #define ACC_REG_BTR_CL_MASK_SJW … /* BRP and BTR register layout for CAN-FD version */ #define ACC_REG_BRP_FD_MASK_BRP … #define ACC_REG_BTR_FD_MASK_TSEG1 … #define ACC_REG_BTR_FD_MASK_TSEG2 … #define ACC_REG_BTR_FD_MASK_SJW … /* 256 BM_MSGs of 32 byte size */ #define ACC_CORE_DMAMSG_SIZE … #define ACC_CORE_DMABUF_SIZE … enum acc_bmmsg_id { … }; /* The struct acc_bmmsg_* structure declarations that follow here provide * access to the ring buffer of bus master messages maintained by the FPGA * bus master engine. All bus master messages have the same size of * ACC_CORE_DMAMSG_SIZE and a minimum alignment of ACC_CORE_DMAMSG_SIZE in * memory. * * All structure members are natural aligned. Therefore we should not need * a __packed attribute. All struct acc_bmmsg_* declarations have at least * reserved* members to fill the structure to the full ACC_CORE_DMAMSG_SIZE. * * A failure of this property due padding will be detected at compile time * by static_assert(sizeof(union acc_bmmsg) == ACC_CORE_DMAMSG_SIZE). */ struct acc_bmmsg_rxtxdone { … }; struct acc_bmmsg_txabort { … }; struct acc_bmmsg_overrun { … }; struct acc_bmmsg_buserr { … }; struct acc_bmmsg_errstatechange { … }; struct acc_bmmsg_timeslice { … }; struct acc_bmmsg_hwtimer { … }; struct acc_bmmsg_hotplug { … }; acc_bmmsg; /* Check size of union acc_bmmsg to be of expected size. */ static_assert(…); struct acc_bmfifo { … }; struct acc_core { … }; struct acc_ov { … }; struct acc_net_priv { … }; static inline u32 acc_read32(struct acc_core *core, unsigned short offs) { … } static inline void acc_write32(struct acc_core *core, unsigned short offs, u32 v) { … } static inline void acc_write32_noswap(struct acc_core *core, unsigned short offs, u32 v) { … } static inline void acc_set_bits(struct acc_core *core, unsigned short offs, u32 mask) { … } static inline void acc_clear_bits(struct acc_core *core, unsigned short offs, u32 mask) { … } static inline int acc_resetmode_entered(struct acc_core *core) { … } static inline u32 acc_ov_read32(struct acc_ov *ov, unsigned short offs) { … } static inline void acc_ov_write32(struct acc_ov *ov, unsigned short offs, u32 v) { … } static inline void acc_ov_set_bits(struct acc_ov *ov, unsigned short offs, u32 b) { … } static inline void acc_ov_clear_bits(struct acc_ov *ov, unsigned short offs, u32 b) { … } static inline void acc_reset_fpga(struct acc_ov *ov) { … } void acc_init_ov(struct acc_ov *ov, struct device *dev); void acc_init_bm_ptr(struct acc_ov *ov, struct acc_core *cores, const void *mem); int acc_open(struct net_device *netdev); int acc_close(struct net_device *netdev); netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev); int acc_get_berr_counter(const struct net_device *netdev, struct can_berr_counter *bec); int acc_set_mode(struct net_device *netdev, enum can_mode mode); int acc_set_bittiming(struct net_device *netdev); irqreturn_t acc_card_interrupt(struct acc_ov *ov, struct acc_core *cores);
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