// SPDX-License-Identifier: GPL-2.0 /* * Driver for Renesas R-Car MIPI CSI-2 Receiver * * Copyright (C) 2018 Renesas Electronics Corp. */ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/sys_soc.h> #include <media/mipi-csi2.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-mc.h> #include <media/v4l2-subdev.h> struct rcar_csi2; /* Register offsets and bits */ /* Control Timing Select */ #define TREF_REG … #define TREF_TREF … /* Software Reset */ #define SRST_REG … #define SRST_SRST … /* PHY Operation Control */ #define PHYCNT_REG … #define PHYCNT_SHUTDOWNZ … #define PHYCNT_RSTZ … #define PHYCNT_ENABLECLK … #define PHYCNT_ENABLE_3 … #define PHYCNT_ENABLE_2 … #define PHYCNT_ENABLE_1 … #define PHYCNT_ENABLE_0 … /* Checksum Control */ #define CHKSUM_REG … #define CHKSUM_ECC_EN … #define CHKSUM_CRC_EN … /* * Channel Data Type Select * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 */ #define VCDT_REG … #define VCDT2_REG … #define VCDT_VCDTN_EN … #define VCDT_SEL_VC(n) … #define VCDT_SEL_DTN_ON … #define VCDT_SEL_DT(n) … /* Frame Data Type Select */ #define FRDT_REG … /* Field Detection Control */ #define FLD_REG … #define FLD_FLD_NUM(n) … #define FLD_DET_SEL(n) … #define FLD_FLD_EN4 … #define FLD_FLD_EN3 … #define FLD_FLD_EN2 … #define FLD_FLD_EN … /* Automatic Standby Control */ #define ASTBY_REG … /* Long Data Type Setting 0 */ #define LNGDT0_REG … /* Long Data Type Setting 1 */ #define LNGDT1_REG … /* Interrupt Enable */ #define INTEN_REG … #define INTEN_INT_AFIFO_OF … #define INTEN_INT_ERRSOTHS … #define INTEN_INT_ERRSOTSYNCHS … /* Interrupt Source Mask */ #define INTCLOSE_REG … /* Interrupt Status Monitor */ #define INTSTATE_REG … #define INTSTATE_INT_ULPS_START … #define INTSTATE_INT_ULPS_END … /* Interrupt Error Status Monitor */ #define INTERRSTATE_REG … /* Short Packet Data */ #define SHPDAT_REG … /* Short Packet Count */ #define SHPCNT_REG … /* LINK Operation Control */ #define LINKCNT_REG … #define LINKCNT_MONITOR_EN … #define LINKCNT_REG_MONI_PACT_EN … #define LINKCNT_ICLK_NONSTOP … /* Lane Swap */ #define LSWAP_REG … #define LSWAP_L3SEL(n) … #define LSWAP_L2SEL(n) … #define LSWAP_L1SEL(n) … #define LSWAP_L0SEL(n) … /* PHY Test Interface Write Register */ #define PHTW_REG … #define PHTW_DWEN … #define PHTW_TESTDIN_DATA(n) … #define PHTW_CWEN … #define PHTW_TESTDIN_CODE(n) … #define PHYFRX_REG … #define PHYFRX_FORCERX_MODE_3 … #define PHYFRX_FORCERX_MODE_2 … #define PHYFRX_FORCERX_MODE_1 … #define PHYFRX_FORCERX_MODE_0 … /* V4H BASE registers */ #define V4H_N_LANES_REG … #define V4H_CSI2_RESETN_REG … #define V4H_PHY_MODE_REG … #define V4H_PHY_SHUTDOWNZ_REG … #define V4H_DPHY_RSTZ_REG … #define V4H_FLDC_REG … #define V4H_FLDD_REG … #define V4H_IDIC_REG … #define V4H_PHY_EN_REG … #define V4H_ST_PHYST_REG … #define V4H_ST_PHYST_ST_PHY_READY … #define V4H_ST_PHYST_ST_STOPSTATE_3 … #define V4H_ST_PHYST_ST_STOPSTATE_2 … #define V4H_ST_PHYST_ST_STOPSTATE_1 … #define V4H_ST_PHYST_ST_STOPSTATE_0 … /* V4H PPI registers */ #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) … #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG … #define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG … #define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG … #define V4H_PPI_RW_LPDCOCAL_NREF_REG … #define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG … #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG … #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG … #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG … #define V4H_PPI_RW_COMMON_CFG_REG … #define V4H_PPI_RW_TERMCAL_CFG_0_REG … #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG … /* V4H CORE registers */ #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) … #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) … #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) … #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) … #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) … #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) … #define V4H_CORE_DIG_RW_COMMON_REG(n) … #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) … #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG … #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG … /* V4H C-PHY */ #define V4H_CORE_DIG_RW_TRIO0_REG(n) … #define V4H_CORE_DIG_RW_TRIO1_REG(n) … #define V4H_CORE_DIG_RW_TRIO2_REG(n) … #define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG … #define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) … #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG … #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) … #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG … #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) … struct rcsi2_cphy_setting { … }; static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = …; struct phtw_value { … }; struct rcsi2_mbps_reg { … }; static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = …; static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = …; static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = …; /* PHY Test Interface Clear */ #define PHTC_REG … #define PHTC_TESTCLR … /* PHY Frequency Control */ #define PHYPLL_REG … #define PHYPLL_HSFREQRANGE(n) … static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = …; static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = …; static const struct rcsi2_mbps_reg hsfreqrange_m3w[] = …; /* PHY ESC Error Monitor */ #define PHEERM_REG … /* PHY Clock Lane Monitor */ #define PHCLM_REG … #define PHCLM_STOPSTATECKL … /* PHY Data Lane Monitor */ #define PHDLM_REG … /* CSI0CLK Frequency Configuration Preset Register */ #define CSI0CLKFCPR_REG … #define CSI0CLKFREQRANGE(n) … struct rcar_csi2_format { … }; static const struct rcar_csi2_format rcar_csi2_formats[] = …; static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) { … } enum rcar_csi2_pads { … }; struct rcar_csi2_info { … }; struct rcar_csi2 { … }; static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) { … } static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) { … } static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv) { … } static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) { … } static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) { … } static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) { … } static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) { … } static void rcsi2_enter_standby(struct rcar_csi2 *priv) { … } static int rcsi2_exit_standby(struct rcar_csi2 *priv) { … } static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, unsigned int lanes) { … } static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) { … } static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, unsigned int lanes) { … } static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, unsigned int *lanes) { … } static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) { … } static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match) { … } static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps) { … } static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) { … } static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) { … } static void rcsi2_stop(struct rcar_csi2 *priv) { … } static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable) { … } static int rcsi2_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_format *format) { … } static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = …; static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = …; static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = …; static int rcsi2_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *state) { … } static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = …; static irqreturn_t rcsi2_irq(int irq, void *data) { … } static irqreturn_t rcsi2_irq_thread(int irq, void *data) { … } /* ----------------------------------------------------------------------------- * Async handling and registration of subdevices and links. */ static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, struct v4l2_subdev *subdev, struct v4l2_async_connection *asc) { … } static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, struct v4l2_subdev *subdev, struct v4l2_async_connection *asc) { … } static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = …; static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, struct v4l2_fwnode_endpoint *vep) { … } static int rcsi2_parse_dt(struct rcar_csi2 *priv) { … } /* ----------------------------------------------------------------------------- * PHTW initialization sequences. * * NOTE: Magic values are from the datasheet and lack documentation. */ static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code) { … } static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, const struct phtw_value *values) { … } static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, const struct rcsi2_mbps_reg *values, u16 code) { … } static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) { … } static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) { … } static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) { … } static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) { … } static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) { … } static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, unsigned int mbps) { … } /* ----------------------------------------------------------------------------- * Platform Device Driver. */ static int rcsi2_link_setup(struct media_entity *entity, const struct media_pad *local, const struct media_pad *remote, u32 flags) { … } static const struct media_entity_operations rcar_csi2_entity_ops = …; static int rcsi2_probe_resources(struct rcar_csi2 *priv, struct platform_device *pdev) { … } static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = …; static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = …; static const struct of_device_id rcar_csi2_of_table[] = …; MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); static const struct soc_device_attribute r8a7795[] = …; static int rcsi2_probe(struct platform_device *pdev) { … } static void rcsi2_remove(struct platform_device *pdev) { … } static struct platform_driver rcar_csi2_pdrv = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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