// SPDX-License-Identifier: GPL-2.0 /* TI ADS1298 chip family driver * Copyright (C) 2023 - 2024 Topic Embedded Products */ #include <linux/bitfield.h> #include <linux/cleanup.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/gpio/consumer.h> #include <linux/log2.h> #include <linux/math.h> #include <linux/module.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/slab.h> #include <linux/spi/spi.h> #include <linux/units.h> #include <linux/iio/iio.h> #include <linux/iio/buffer.h> #include <linux/iio/kfifo_buf.h> #include <linux/unaligned.h> /* Commands */ #define ADS1298_CMD_WAKEUP … #define ADS1298_CMD_STANDBY … #define ADS1298_CMD_RESET … #define ADS1298_CMD_START … #define ADS1298_CMD_STOP … #define ADS1298_CMD_RDATAC … #define ADS1298_CMD_SDATAC … #define ADS1298_CMD_RDATA … #define ADS1298_CMD_RREG … #define ADS1298_CMD_WREG … /* Registers */ #define ADS1298_REG_ID … #define ADS1298_MASK_ID_FAMILY … #define ADS1298_MASK_ID_CHANNELS … #define ADS1298_ID_FAMILY_ADS129X … #define ADS1298_ID_FAMILY_ADS129XR … #define ADS1298_REG_CONFIG1 … #define ADS1298_MASK_CONFIG1_HR … #define ADS1298_MASK_CONFIG1_DR … #define ADS1298_SHIFT_DR_HR … #define ADS1298_SHIFT_DR_LP … #define ADS1298_LOWEST_DR … #define ADS1298_REG_CONFIG2 … #define ADS1298_MASK_CONFIG2_RESERVED … #define ADS1298_MASK_CONFIG2_WCT_CHOP … #define ADS1298_MASK_CONFIG2_INT_TEST … #define ADS1298_MASK_CONFIG2_TEST_AMP … #define ADS1298_MASK_CONFIG2_TEST_FREQ_DC … #define ADS1298_MASK_CONFIG2_TEST_FREQ_SLOW … #define ADS1298_MASK_CONFIG2_TEST_FREQ_FAST … #define ADS1298_REG_CONFIG3 … #define ADS1298_MASK_CONFIG3_PWR_REFBUF … #define ADS1298_MASK_CONFIG3_RESERVED … #define ADS1298_MASK_CONFIG3_VREF_4V … #define ADS1298_REG_LOFF … #define ADS1298_REG_CHnSET(n) … #define ADS1298_MASK_CH_PD … #define ADS1298_MASK_CH_PGA … #define ADS1298_MASK_CH_MUX … #define ADS1298_REG_LOFF_STATP … #define ADS1298_REG_LOFF_STATN … #define ADS1298_REG_CONFIG4 … #define ADS1298_MASK_CONFIG4_SINGLE_SHOT … #define ADS1298_REG_WCT1 … #define ADS1298_REG_WCT2 … #define ADS1298_MAX_CHANNELS … #define ADS1298_BITS_PER_SAMPLE … #define ADS1298_CLK_RATE_HZ … #define ADS1298_CLOCKS_TO_USECS(x) … /* * Read/write register commands require 4 clocks to decode, for speeds above * 2x the clock rate, this would require extra time between the command byte and * the data. Much simpler is to just limit the SPI transfer speed while doing * register access. */ #define ADS1298_SPI_BUS_SPEED_SLOW … /* For reading and writing registers, we need a 3-byte buffer */ #define ADS1298_SPI_CMD_BUFFER_SIZE … /* Outputs status word and 'n' 24-bit samples, plus the command byte */ #define ADS1298_SPI_RDATA_BUFFER_SIZE(n) … #define ADS1298_SPI_RDATA_BUFFER_SIZE_MAX … struct ads1298_private { … }; /* Three bytes per sample in RX buffer, starting at offset 4 */ #define ADS1298_OFFSET_IN_RX_BUFFER(index) … #define ADS1298_CHAN(index) … static const struct iio_chan_spec ads1298_channels[] = …; static int ads1298_write_cmd(struct ads1298_private *priv, u8 command) { … } static int ads1298_read_one(struct ads1298_private *priv, int chan_index) { … } static int ads1298_get_samp_freq(struct ads1298_private *priv, int *val) { … } static int ads1298_set_samp_freq(struct ads1298_private *priv, int val) { … } static const u8 ads1298_pga_settings[] = …; static int ads1298_get_scale(struct ads1298_private *priv, int channel, int *val, int *val2) { … } static int ads1298_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { … } static int ads1298_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { … } static int ads1298_reg_write(void *context, unsigned int reg, unsigned int val) { … } static int ads1298_reg_read(void *context, unsigned int reg, unsigned int *val) { … } static int ads1298_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { … } static void ads1298_rdata_unmark_busy(struct ads1298_private *priv) { … } static int ads1298_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { … } static const struct iio_info ads1298_info = …; static void ads1298_rdata_release_busy_or_restart(struct ads1298_private *priv) { … } /* Called from SPI completion interrupt handler */ static void ads1298_rdata_complete(void *context) { … } static irqreturn_t ads1298_interrupt(int irq, void *dev_id) { struct iio_dev *indio_dev = dev_id; struct ads1298_private *priv = iio_priv(indio_dev); unsigned int wasbusy; guard(spinlock_irqsave)(&priv->irq_busy_lock); wasbusy = priv->rdata_xfer_busy++; /* When no SPI transfer in transit, start one now */ if (!wasbusy) spi_async(priv->spi, &priv->rdata_msg); return IRQ_HANDLED; }; static int ads1298_buffer_postenable(struct iio_dev *indio_dev) { … } static int ads1298_buffer_predisable(struct iio_dev *indio_dev) { … } static const struct iio_buffer_setup_ops ads1298_setup_ops = …; static void ads1298_reg_disable(void *reg) { … } static const struct regmap_range ads1298_regmap_volatile_range[] = …; static const struct regmap_access_table ads1298_regmap_volatile = …; static const struct regmap_config ads1298_regmap_config = …; static int ads1298_init(struct iio_dev *indio_dev) { … } static int ads1298_probe(struct spi_device *spi) { … } static const struct spi_device_id ads1298_id[] = …; MODULE_DEVICE_TABLE(spi, ads1298_id); static const struct of_device_id ads1298_of_table[] = …; MODULE_DEVICE_TABLE(of, ads1298_of_table); static struct spi_driver ads1298_driver = …; module_spi_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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