/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef LINUX_SSB_CHIPCO_H_ #define LINUX_SSB_CHIPCO_H_ /* SonicsSiliconBackplane CHIPCOMMON core hardware definitions * * The chipcommon core provides chip identification, SB control, * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, * gpio interface, extbus, and support for serial and parallel flashes. * * Copyright 2005, Broadcom Corporation * Copyright 2006, Michael Buesch <[email protected]> */ /** ChipCommon core registers. **/ #define SSB_CHIPCO_CHIPID … #define SSB_CHIPCO_IDMASK … #define SSB_CHIPCO_REVMASK … #define SSB_CHIPCO_REVSHIFT … #define SSB_CHIPCO_PACKMASK … #define SSB_CHIPCO_PACKSHIFT … #define SSB_CHIPCO_NRCORESMASK … #define SSB_CHIPCO_NRCORESSHIFT … #define SSB_CHIPCO_CAP … #define SSB_CHIPCO_CAP_NRUART … #define SSB_CHIPCO_CAP_MIPSEB … #define SSB_CHIPCO_CAP_UARTCLK … #define SSB_CHIPCO_CAP_UARTCLK_INT … #define SSB_CHIPCO_CAP_UARTGPIO … #define SSB_CHIPCO_CAP_EXTBUS … #define SSB_CHIPCO_CAP_FLASHT … #define SSB_CHIPCO_FLASHT_NONE … #define SSB_CHIPCO_FLASHT_STSER … #define SSB_CHIPCO_FLASHT_ATSER … #define SSB_CHIPCO_FLASHT_PARA … #define SSB_CHIPCO_CAP_PLLT … #define SSB_PLLTYPE_NONE … #define SSB_PLLTYPE_1 … #define SSB_PLLTYPE_2 … #define SSB_PLLTYPE_3 … #define SSB_PLLTYPE_4 … #define SSB_PLLTYPE_5 … #define SSB_PLLTYPE_6 … #define SSB_PLLTYPE_7 … #define SSB_CHIPCO_CAP_PCTL … #define SSB_CHIPCO_CAP_OTPS … #define SSB_CHIPCO_CAP_OTPS_SHIFT … #define SSB_CHIPCO_CAP_OTPS_BASE … #define SSB_CHIPCO_CAP_JTAGM … #define SSB_CHIPCO_CAP_BROM … #define SSB_CHIPCO_CAP_64BIT … #define SSB_CHIPCO_CAP_PMU … #define SSB_CHIPCO_CAP_ECI … #define SSB_CHIPCO_CAP_SPROM … #define SSB_CHIPCO_CORECTL … #define SSB_CHIPCO_CORECTL_UARTCLK0 … #define SSB_CHIPCO_CORECTL_SE … #define SSB_CHIPCO_CORECTL_UARTCLKEN … #define SSB_CHIPCO_BIST … #define SSB_CHIPCO_OTPS … #define SSB_CHIPCO_OTPS_PROGFAIL … #define SSB_CHIPCO_OTPS_PROTECT … #define SSB_CHIPCO_OTPS_HW_PROTECT … #define SSB_CHIPCO_OTPS_SW_PROTECT … #define SSB_CHIPCO_OTPS_CID_PROTECT … #define SSB_CHIPCO_OTPC … #define SSB_CHIPCO_OTPC_RECWAIT … #define SSB_CHIPCO_OTPC_PROGWAIT … #define SSB_CHIPCO_OTPC_PRW_SHIFT … #define SSB_CHIPCO_OTPC_MAXFAIL … #define SSB_CHIPCO_OTPC_VSEL … #define SSB_CHIPCO_OTPC_SELVL … #define SSB_CHIPCO_OTPP … #define SSB_CHIPCO_OTPP_COL … #define SSB_CHIPCO_OTPP_ROW … #define SSB_CHIPCO_OTPP_ROW_SHIFT … #define SSB_CHIPCO_OTPP_READERR … #define SSB_CHIPCO_OTPP_VALUE … #define SSB_CHIPCO_OTPP_READ … #define SSB_CHIPCO_OTPP_START … #define SSB_CHIPCO_OTPP_BUSY … #define SSB_CHIPCO_IRQSTAT … #define SSB_CHIPCO_IRQMASK … #define SSB_CHIPCO_IRQ_GPIO … #define SSB_CHIPCO_IRQ_EXT … #define SSB_CHIPCO_IRQ_WDRESET … #define SSB_CHIPCO_CHIPCTL … #define SSB_CHIPCO_CHIPSTAT … #define SSB_CHIPCO_JCMD … #define SSB_CHIPCO_JCMD_START … #define SSB_CHIPCO_JCMD_BUSY … #define SSB_CHIPCO_JCMD_PAUSE … #define SSB_CHIPCO_JCMD0_ACC_MASK … #define SSB_CHIPCO_JCMD0_ACC_IRDR … #define SSB_CHIPCO_JCMD0_ACC_DR … #define SSB_CHIPCO_JCMD0_ACC_IR … #define SSB_CHIPCO_JCMD0_ACC_RESET … #define SSB_CHIPCO_JCMD0_ACC_IRPDR … #define SSB_CHIPCO_JCMD0_ACC_PDR … #define SSB_CHIPCO_JCMD0_IRW_MASK … #define SSB_CHIPCO_JCMD_ACC_MASK … #define SSB_CHIPCO_JCMD_ACC_IRDR … #define SSB_CHIPCO_JCMD_ACC_DR … #define SSB_CHIPCO_JCMD_ACC_IR … #define SSB_CHIPCO_JCMD_ACC_RESET … #define SSB_CHIPCO_JCMD_ACC_IRPDR … #define SSB_CHIPCO_JCMD_ACC_PDR … #define SSB_CHIPCO_JCMD_IRW_MASK … #define SSB_CHIPCO_JCMD_IRW_SHIFT … #define SSB_CHIPCO_JCMD_DRW_MASK … #define SSB_CHIPCO_JIR … #define SSB_CHIPCO_JDR … #define SSB_CHIPCO_JCTL … #define SSB_CHIPCO_JCTL_FORCE_CLK … #define SSB_CHIPCO_JCTL_EXT_EN … #define SSB_CHIPCO_JCTL_EN … #define SSB_CHIPCO_FLASHCTL … #define SSB_CHIPCO_FLASHCTL_START … #define SSB_CHIPCO_FLASHCTL_BUSY … #define SSB_CHIPCO_FLASHADDR … #define SSB_CHIPCO_FLASHDATA … #define SSB_CHIPCO_BCAST_ADDR … #define SSB_CHIPCO_BCAST_DATA … #define SSB_CHIPCO_GPIOPULLUP … #define SSB_CHIPCO_GPIOPULLDOWN … #define SSB_CHIPCO_GPIOIN … #define SSB_CHIPCO_GPIOOUT … #define SSB_CHIPCO_GPIOOUTEN … #define SSB_CHIPCO_GPIOCTL … #define SSB_CHIPCO_GPIOPOL … #define SSB_CHIPCO_GPIOIRQ … #define SSB_CHIPCO_WATCHDOG … #define SSB_CHIPCO_GPIOTIMER … #define SSB_CHIPCO_GPIOTIMER_OFFTIME … #define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT … #define SSB_CHIPCO_GPIOTIMER_ONTIME … #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT … #define SSB_CHIPCO_GPIOTOUTM … #define SSB_CHIPCO_CLOCK_N … #define SSB_CHIPCO_CLOCK_SB … #define SSB_CHIPCO_CLOCK_PCI … #define SSB_CHIPCO_CLOCK_M2 … #define SSB_CHIPCO_CLOCK_MIPS … #define SSB_CHIPCO_CLKDIV … #define SSB_CHIPCO_CLKDIV_SFLASH … #define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT … #define SSB_CHIPCO_CLKDIV_OTP … #define SSB_CHIPCO_CLKDIV_OTP_SHIFT … #define SSB_CHIPCO_CLKDIV_JTAG … #define SSB_CHIPCO_CLKDIV_JTAG_SHIFT … #define SSB_CHIPCO_CLKDIV_UART … #define SSB_CHIPCO_PLLONDELAY … #define SSB_CHIPCO_FREFSELDELAY … #define SSB_CHIPCO_SLOWCLKCTL … #define SSB_CHIPCO_SLOWCLKCTL_SRC … #define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO … #define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL … #define SSB_CHIPCO_SLOECLKCTL_SRC_PCI … #define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ … #define SSB_CHIPCO_SLOWCLKCTL_LPOPD … #define SSB_CHIPCO_SLOWCLKCTL_FSLOW … #define SSB_CHIPCO_SLOWCLKCTL_IPLL … #define SSB_CHIPCO_SLOWCLKCTL_ENXTAL … #define SSB_CHIPCO_SLOWCLKCTL_XTALPU … #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV … #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT … #define SSB_CHIPCO_SYSCLKCTL … #define SSB_CHIPCO_SYSCLKCTL_IDLPEN … #define SSB_CHIPCO_SYSCLKCTL_ALPEN … #define SSB_CHIPCO_SYSCLKCTL_PLLEN … #define SSB_CHIPCO_SYSCLKCTL_FORCEALP … #define SSB_CHIPCO_SYSCLKCTL_FORCEHT … #define SSB_CHIPCO_SYSCLKCTL_CLKDIV … #define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT … #define SSB_CHIPCO_CLKSTSTR … #define SSB_CHIPCO_PCMCIA_CFG … #define SSB_CHIPCO_PCMCIA_MEMWAIT … #define SSB_CHIPCO_PCMCIA_ATTRWAIT … #define SSB_CHIPCO_PCMCIA_IOWAIT … #define SSB_CHIPCO_IDE_CFG … #define SSB_CHIPCO_IDE_MEMWAIT … #define SSB_CHIPCO_IDE_ATTRWAIT … #define SSB_CHIPCO_IDE_IOWAIT … #define SSB_CHIPCO_PROG_CFG … #define SSB_CHIPCO_PROG_WAITCNT … #define SSB_CHIPCO_FLASH_CFG … #define SSB_CHIPCO_FLASH_WAITCNT … #define SSB_CHIPCO_CLKCTLST … #define SSB_CHIPCO_CLKCTLST_FORCEALP … #define SSB_CHIPCO_CLKCTLST_FORCEHT … #define SSB_CHIPCO_CLKCTLST_FORCEILP … #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ … #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ … #define SSB_CHIPCO_CLKCTLST_HWCROFF … #define SSB_CHIPCO_CLKCTLST_HAVEALP … #define SSB_CHIPCO_CLKCTLST_HAVEHT … #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT … #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP … #define SSB_CHIPCO_HW_WORKAROUND … #define SSB_CHIPCO_UART0_DATA … #define SSB_CHIPCO_UART0_IMR … #define SSB_CHIPCO_UART0_FCR … #define SSB_CHIPCO_UART0_LCR … #define SSB_CHIPCO_UART0_MCR … #define SSB_CHIPCO_UART0_LSR … #define SSB_CHIPCO_UART0_MSR … #define SSB_CHIPCO_UART0_SCRATCH … #define SSB_CHIPCO_UART1_DATA … #define SSB_CHIPCO_UART1_IMR … #define SSB_CHIPCO_UART1_FCR … #define SSB_CHIPCO_UART1_LCR … #define SSB_CHIPCO_UART1_MCR … #define SSB_CHIPCO_UART1_LSR … #define SSB_CHIPCO_UART1_MSR … #define SSB_CHIPCO_UART1_SCRATCH … /* PMU registers (rev >= 20) */ #define SSB_CHIPCO_PMU_CTL … #define SSB_CHIPCO_PMU_CTL_ILP_DIV … #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT … #define SSB_CHIPCO_PMU_CTL_PLL_UPD … #define SSB_CHIPCO_PMU_CTL_NOILPONW … #define SSB_CHIPCO_PMU_CTL_HTREQEN … #define SSB_CHIPCO_PMU_CTL_ALPREQEN … #define SSB_CHIPCO_PMU_CTL_XTALFREQ … #define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT … #define SSB_CHIPCO_PMU_CTL_ILPDIVEN … #define SSB_CHIPCO_PMU_CTL_LPOSEL … #define SSB_CHIPCO_PMU_CAP … #define SSB_CHIPCO_PMU_CAP_REVISION … #define SSB_CHIPCO_PMU_STAT … #define SSB_CHIPCO_PMU_STAT_INTPEND … #define SSB_CHIPCO_PMU_STAT_SBCLKST … #define SSB_CHIPCO_PMU_STAT_HAVEALP … #define SSB_CHIPCO_PMU_STAT_HAVEHT … #define SSB_CHIPCO_PMU_STAT_RESINIT … #define SSB_CHIPCO_PMU_RES_STAT … #define SSB_CHIPCO_PMU_RES_PEND … #define SSB_CHIPCO_PMU_TIMER … #define SSB_CHIPCO_PMU_MINRES_MSK … #define SSB_CHIPCO_PMU_MAXRES_MSK … #define SSB_CHIPCO_PMU_RES_TABSEL … #define SSB_CHIPCO_PMU_RES_DEPMSK … #define SSB_CHIPCO_PMU_RES_UPDNTM … #define SSB_CHIPCO_PMU_RES_TIMER … #define SSB_CHIPCO_PMU_CLKSTRETCH … #define SSB_CHIPCO_PMU_WATCHDOG … #define SSB_CHIPCO_PMU_RES_REQTS … #define SSB_CHIPCO_PMU_RES_REQT … #define SSB_CHIPCO_PMU_RES_REQM … #define SSB_CHIPCO_CHIPCTL_ADDR … #define SSB_CHIPCO_CHIPCTL_DATA … #define SSB_CHIPCO_REGCTL_ADDR … #define SSB_CHIPCO_REGCTL_DATA … #define SSB_CHIPCO_PLLCTL_ADDR … #define SSB_CHIPCO_PLLCTL_DATA … /** PMU PLL registers */ /* PMU rev 0 PLL registers */ #define SSB_PMU0_PLLCTL0 … #define SSB_PMU0_PLLCTL0_PDIV_MSK … #define SSB_PMU0_PLLCTL0_PDIV_FREQ … #define SSB_PMU0_PLLCTL1 … #define SSB_PMU0_PLLCTL1_WILD_IMSK … #define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT … #define SSB_PMU0_PLLCTL1_WILD_FMSK … #define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT … #define SSB_PMU0_PLLCTL1_STOPMOD … #define SSB_PMU0_PLLCTL2 … #define SSB_PMU0_PLLCTL2_WILD_IMSKHI … #define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT … /* PMU rev 1 PLL registers */ #define SSB_PMU1_PLLCTL0 … #define SSB_PMU1_PLLCTL0_P1DIV … #define SSB_PMU1_PLLCTL0_P1DIV_SHIFT … #define SSB_PMU1_PLLCTL0_P2DIV … #define SSB_PMU1_PLLCTL0_P2DIV_SHIFT … #define SSB_PMU1_PLLCTL1 … #define SSB_PMU1_PLLCTL1_M1DIV … #define SSB_PMU1_PLLCTL1_M1DIV_SHIFT … #define SSB_PMU1_PLLCTL1_M2DIV … #define SSB_PMU1_PLLCTL1_M2DIV_SHIFT … #define SSB_PMU1_PLLCTL1_M3DIV … #define SSB_PMU1_PLLCTL1_M3DIV_SHIFT … #define SSB_PMU1_PLLCTL1_M4DIV … #define SSB_PMU1_PLLCTL1_M4DIV_SHIFT … #define SSB_PMU1_PLLCTL2 … #define SSB_PMU1_PLLCTL2_M5DIV … #define SSB_PMU1_PLLCTL2_M5DIV_SHIFT … #define SSB_PMU1_PLLCTL2_M6DIV … #define SSB_PMU1_PLLCTL2_M6DIV_SHIFT … #define SSB_PMU1_PLLCTL2_NDIVMODE … #define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT … #define SSB_PMU1_PLLCTL2_NDIVINT … #define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT … #define SSB_PMU1_PLLCTL3 … #define SSB_PMU1_PLLCTL3_NDIVFRAC … #define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT … #define SSB_PMU1_PLLCTL4 … #define SSB_PMU1_PLLCTL5 … #define SSB_PMU1_PLLCTL5_CLKDRV … #define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT … /* BCM4312 PLL resource numbers. */ #define SSB_PMURES_4312_SWITCHER_BURST … #define SSB_PMURES_4312_SWITCHER_PWM … #define SSB_PMURES_4312_PA_REF_LDO … #define SSB_PMURES_4312_CORE_LDO_BURST … #define SSB_PMURES_4312_CORE_LDO_PWM … #define SSB_PMURES_4312_RADIO_LDO … #define SSB_PMURES_4312_ILP_REQUEST … #define SSB_PMURES_4312_BG_FILTBYP … #define SSB_PMURES_4312_TX_FILTBYP … #define SSB_PMURES_4312_RX_FILTBYP … #define SSB_PMURES_4312_XTAL_PU … #define SSB_PMURES_4312_ALP_AVAIL … #define SSB_PMURES_4312_BB_PLL_FILTBYP … #define SSB_PMURES_4312_RF_PLL_FILTBYP … #define SSB_PMURES_4312_HT_AVAIL … /* BCM4325 PLL resource numbers. */ #define SSB_PMURES_4325_BUCK_BOOST_BURST … #define SSB_PMURES_4325_CBUCK_BURST … #define SSB_PMURES_4325_CBUCK_PWM … #define SSB_PMURES_4325_CLDO_CBUCK_BURST … #define SSB_PMURES_4325_CLDO_CBUCK_PWM … #define SSB_PMURES_4325_BUCK_BOOST_PWM … #define SSB_PMURES_4325_ILP_REQUEST … #define SSB_PMURES_4325_ABUCK_BURST … #define SSB_PMURES_4325_ABUCK_PWM … #define SSB_PMURES_4325_LNLDO1_PU … #define SSB_PMURES_4325_LNLDO2_PU … #define SSB_PMURES_4325_LNLDO3_PU … #define SSB_PMURES_4325_LNLDO4_PU … #define SSB_PMURES_4325_XTAL_PU … #define SSB_PMURES_4325_ALP_AVAIL … #define SSB_PMURES_4325_RX_PWRSW_PU … #define SSB_PMURES_4325_TX_PWRSW_PU … #define SSB_PMURES_4325_RFPLL_PWRSW_PU … #define SSB_PMURES_4325_LOGEN_PWRSW_PU … #define SSB_PMURES_4325_AFE_PWRSW_PU … #define SSB_PMURES_4325_BBPLL_PWRSW_PU … #define SSB_PMURES_4325_HT_AVAIL … /* BCM4328 PLL resource numbers. */ #define SSB_PMURES_4328_EXT_SWITCHER_PWM … #define SSB_PMURES_4328_BB_SWITCHER_PWM … #define SSB_PMURES_4328_BB_SWITCHER_BURST … #define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST … #define SSB_PMURES_4328_ILP_REQUEST … #define SSB_PMURES_4328_RADIO_SWITCHER_PWM … #define SSB_PMURES_4328_RADIO_SWITCHER_BURST … #define SSB_PMURES_4328_ROM_SWITCH … #define SSB_PMURES_4328_PA_REF_LDO … #define SSB_PMURES_4328_RADIO_LDO … #define SSB_PMURES_4328_AFE_LDO … #define SSB_PMURES_4328_PLL_LDO … #define SSB_PMURES_4328_BG_FILTBYP … #define SSB_PMURES_4328_TX_FILTBYP … #define SSB_PMURES_4328_RX_FILTBYP … #define SSB_PMURES_4328_XTAL_PU … #define SSB_PMURES_4328_XTAL_EN … #define SSB_PMURES_4328_BB_PLL_FILTBYP … #define SSB_PMURES_4328_RF_PLL_FILTBYP … #define SSB_PMURES_4328_BB_PLL_PU … /* BCM5354 PLL resource numbers. */ #define SSB_PMURES_5354_EXT_SWITCHER_PWM … #define SSB_PMURES_5354_BB_SWITCHER_PWM … #define SSB_PMURES_5354_BB_SWITCHER_BURST … #define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST … #define SSB_PMURES_5354_ILP_REQUEST … #define SSB_PMURES_5354_RADIO_SWITCHER_PWM … #define SSB_PMURES_5354_RADIO_SWITCHER_BURST … #define SSB_PMURES_5354_ROM_SWITCH … #define SSB_PMURES_5354_PA_REF_LDO … #define SSB_PMURES_5354_RADIO_LDO … #define SSB_PMURES_5354_AFE_LDO … #define SSB_PMURES_5354_PLL_LDO … #define SSB_PMURES_5354_BG_FILTBYP … #define SSB_PMURES_5354_TX_FILTBYP … #define SSB_PMURES_5354_RX_FILTBYP … #define SSB_PMURES_5354_XTAL_PU … #define SSB_PMURES_5354_XTAL_EN … #define SSB_PMURES_5354_BB_PLL_FILTBYP … #define SSB_PMURES_5354_RF_PLL_FILTBYP … #define SSB_PMURES_5354_BB_PLL_PU … /** Chip specific Chip-Status register contents. */ #define SSB_CHIPCO_CHST_4322_SPROM_EXISTS … #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL … #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL … #define SSB_CHIPCO_CHST_4325_SPROM_SEL … #define SSB_CHIPCO_CHST_4325_OTP_SEL … #define SSB_CHIPCO_CHST_4325_OTP_PWRDN … #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE … #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT … #define SSB_CHIPCO_CHST_4325_RCAL_VALID … #define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT … #define SSB_CHIPCO_CHST_4325_RCAL_VALUE … #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT … #define SSB_CHIPCO_CHST_4325_PMUTOP_2B … /** Macros to determine SPROM presence based on Chip-Status register. */ #define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) … #define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) … #define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) … /** Clockcontrol masks and values **/ /* SSB_CHIPCO_CLOCK_N */ #define SSB_CHIPCO_CLK_N1 … #define SSB_CHIPCO_CLK_N2 … #define SSB_CHIPCO_CLK_N2_SHIFT … #define SSB_CHIPCO_CLK_PLLC … #define SSB_CHIPCO_CLK_PLLC_SHIFT … /* SSB_CHIPCO_CLOCK_SB/PCI/UART */ #define SSB_CHIPCO_CLK_M1 … #define SSB_CHIPCO_CLK_M2 … #define SSB_CHIPCO_CLK_M2_SHIFT … #define SSB_CHIPCO_CLK_M3 … #define SSB_CHIPCO_CLK_M3_SHIFT … #define SSB_CHIPCO_CLK_MC … #define SSB_CHIPCO_CLK_MC_SHIFT … /* N3M Clock control magic field values */ #define SSB_CHIPCO_CLK_F6_2 … #define SSB_CHIPCO_CLK_F6_3 … #define SSB_CHIPCO_CLK_F6_4 … #define SSB_CHIPCO_CLK_F6_5 … #define SSB_CHIPCO_CLK_F6_6 … #define SSB_CHIPCO_CLK_F6_7 … #define SSB_CHIPCO_CLK_F5_BIAS … #define SSB_CHIPCO_CLK_MC_BYPASS … #define SSB_CHIPCO_CLK_MC_M1 … #define SSB_CHIPCO_CLK_MC_M1M2 … #define SSB_CHIPCO_CLK_MC_M1M2M3 … #define SSB_CHIPCO_CLK_MC_M1M3 … /* Type 2 Clock control magic field values */ #define SSB_CHIPCO_CLK_T2_BIAS … #define SSB_CHIPCO_CLK_T2M2_BIAS … #define SSB_CHIPCO_CLK_T2MC_M1BYP … #define SSB_CHIPCO_CLK_T2MC_M2BYP … #define SSB_CHIPCO_CLK_T2MC_M3BYP … /* Type 6 Clock control magic field values */ #define SSB_CHIPCO_CLK_T6_MMASK … #define SSB_CHIPCO_CLK_T6_M0 … #define SSB_CHIPCO_CLK_T6_M1 … #define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) … /* Common clock base */ #define SSB_CHIPCO_CLK_BASE1 … #define SSB_CHIPCO_CLK_BASE2 … /* Clock control values for 200Mhz in 5350 */ #define SSB_CHIPCO_CLK_5350_N … #define SSB_CHIPCO_CLK_5350_M … /** Bits in the config registers **/ #define SSB_CHIPCO_CFG_EN … #define SSB_CHIPCO_CFG_EXTM … #define SSB_CHIPCO_CFG_EXTM_ASYNC … #define SSB_CHIPCO_CFG_EXTM_SYNC … #define SSB_CHIPCO_CFG_EXTM_PCMCIA … #define SSB_CHIPCO_CFG_EXTM_IDE … #define SSB_CHIPCO_CFG_DS16 … #define SSB_CHIPCO_CFG_CLKDIV … #define SSB_CHIPCO_CFG_CLKEN … #define SSB_CHIPCO_CFG_BSTRO … /** Flash-specific control/status values */ /* flashcontrol opcodes for ST flashes */ #define SSB_CHIPCO_FLASHCTL_ST_WREN … #define SSB_CHIPCO_FLASHCTL_ST_WRDIS … #define SSB_CHIPCO_FLASHCTL_ST_RDSR … #define SSB_CHIPCO_FLASHCTL_ST_WRSR … #define SSB_CHIPCO_FLASHCTL_ST_READ … #define SSB_CHIPCO_FLASHCTL_ST_PP … #define SSB_CHIPCO_FLASHCTL_ST_SE … #define SSB_CHIPCO_FLASHCTL_ST_BE … #define SSB_CHIPCO_FLASHCTL_ST_DP … #define SSB_CHIPCO_FLASHCTL_ST_RES … #define SSB_CHIPCO_FLASHCTL_ST_CSA … #define SSB_CHIPCO_FLASHCTL_ST_SSE … /* Status register bits for ST flashes */ #define SSB_CHIPCO_FLASHSTA_ST_WIP … #define SSB_CHIPCO_FLASHSTA_ST_WEL … #define SSB_CHIPCO_FLASHSTA_ST_BP … #define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT … #define SSB_CHIPCO_FLASHSTA_ST_SRWD … /* flashcontrol opcodes for Atmel flashes */ #define SSB_CHIPCO_FLASHCTL_AT_READ … #define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ … #define SSB_CHIPCO_FLASHCTL_AT_STATUS … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM … #define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE … #define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE … #define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM … #define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM … /* Status register bits for Atmel flashes */ #define SSB_CHIPCO_FLASHSTA_AT_READY … #define SSB_CHIPCO_FLASHSTA_AT_MISMATCH … #define SSB_CHIPCO_FLASHSTA_AT_ID … #define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT … /** OTP **/ /* OTP regions */ #define SSB_CHIPCO_OTP_HW_REGION … #define SSB_CHIPCO_OTP_SW_REGION … #define SSB_CHIPCO_OTP_CID_REGION … /* OTP regions (Byte offsets from otp size) */ #define SSB_CHIPCO_OTP_SWLIM_OFF … #define SSB_CHIPCO_OTP_CIDBASE_OFF … #define SSB_CHIPCO_OTP_CIDLIM_OFF … /* Predefined OTP words (Word offset from otp size) */ #define SSB_CHIPCO_OTP_BOUNDARY_OFF … #define SSB_CHIPCO_OTP_HWSIGN_OFF … #define SSB_CHIPCO_OTP_SWSIGN_OFF … #define SSB_CHIPCO_OTP_CIDSIGN_OFF … #define SSB_CHIPCO_OTP_CID_OFF … #define SSB_CHIPCO_OTP_PKG_OFF … #define SSB_CHIPCO_OTP_FID_OFF … #define SSB_CHIPCO_OTP_RSV_OFF … #define SSB_CHIPCO_OTP_LIM_OFF … #define SSB_CHIPCO_OTP_SIGNATURE … #define SSB_CHIPCO_OTP_MAGIC … struct ssb_device; struct ssb_serial_port; /* Data for the PMU, if available. * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU) */ struct ssb_chipcommon_pmu { … }; struct ssb_chipcommon { … }; static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) { … } /* Register access */ #define chipco_read32(cc, offset) … #define chipco_write32(cc, offset, val) … #define chipco_mask32(cc, offset, mask) … #define chipco_set32(cc, offset, set) … #define chipco_maskset32(cc, offset, mask, set) … extern void ssb_chipcommon_init(struct ssb_chipcommon *cc); extern void ssb_chipco_suspend(struct ssb_chipcommon *cc); extern void ssb_chipco_resume(struct ssb_chipcommon *cc); extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m); extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m); extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc, unsigned long ns_per_cycle); enum ssb_clkmode { … }; extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, enum ssb_clkmode mode); extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks); void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask); /* Chipcommon GPIO pin access. */ u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask); u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value); u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value); #ifdef CONFIG_SSB_SERIAL extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, struct ssb_serial_port *ports); #endif /* CONFIG_SSB_SERIAL */ /* PMU support */ extern void ssb_pmu_init(struct ssb_chipcommon *cc); enum ssb_pmu_ldo_volt_id { … }; void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, enum ssb_pmu_ldo_volt_id id, u32 voltage); void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid); #endif /* LINUX_SSB_CHIPCO_H_ */
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