// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com * * CPU frequency scaling for S5PC110/S5PV210 */ #define pr_fmt(fmt) … #include <linux/types.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/cpufreq.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/reboot.h> #include <linux/regulator/consumer.h> static void __iomem *clk_base; static void __iomem *dmc_base[2]; #define S5P_CLKREG(x) … #define S5P_APLL_LOCK … #define S5P_APLL_CON … #define S5P_CLK_SRC0 … #define S5P_CLK_SRC2 … #define S5P_CLK_DIV0 … #define S5P_CLK_DIV2 … #define S5P_CLK_DIV6 … #define S5P_CLKDIV_STAT0 … #define S5P_CLKDIV_STAT1 … #define S5P_CLKMUX_STAT0 … #define S5P_CLKMUX_STAT1 … #define S5P_ARM_MCS_CON … /* CLKSRC0 */ #define S5P_CLKSRC0_MUX200_SHIFT … #define S5P_CLKSRC0_MUX200_MASK … #define S5P_CLKSRC0_MUX166_MASK … #define S5P_CLKSRC0_MUX133_MASK … /* CLKSRC2 */ #define S5P_CLKSRC2_G3D_SHIFT … #define S5P_CLKSRC2_G3D_MASK … #define S5P_CLKSRC2_MFC_SHIFT … #define S5P_CLKSRC2_MFC_MASK … /* CLKDIV0 */ #define S5P_CLKDIV0_APLL_SHIFT … #define S5P_CLKDIV0_APLL_MASK … #define S5P_CLKDIV0_A2M_SHIFT … #define S5P_CLKDIV0_A2M_MASK … #define S5P_CLKDIV0_HCLK200_SHIFT … #define S5P_CLKDIV0_HCLK200_MASK … #define S5P_CLKDIV0_PCLK100_SHIFT … #define S5P_CLKDIV0_PCLK100_MASK … #define S5P_CLKDIV0_HCLK166_SHIFT … #define S5P_CLKDIV0_HCLK166_MASK … #define S5P_CLKDIV0_PCLK83_SHIFT … #define S5P_CLKDIV0_PCLK83_MASK … #define S5P_CLKDIV0_HCLK133_SHIFT … #define S5P_CLKDIV0_HCLK133_MASK … #define S5P_CLKDIV0_PCLK66_SHIFT … #define S5P_CLKDIV0_PCLK66_MASK … /* CLKDIV2 */ #define S5P_CLKDIV2_G3D_SHIFT … #define S5P_CLKDIV2_G3D_MASK … #define S5P_CLKDIV2_MFC_SHIFT … #define S5P_CLKDIV2_MFC_MASK … /* CLKDIV6 */ #define S5P_CLKDIV6_ONEDRAM_SHIFT … #define S5P_CLKDIV6_ONEDRAM_MASK … static struct clk *dmc0_clk; static struct clk *dmc1_clk; static DEFINE_MUTEX(set_freq_lock); /* APLL M,P,S values for 1G/800Mhz */ #define APLL_VAL_1000 … #define APLL_VAL_800 … /* Use 800MHz when entering sleep mode */ #define SLEEP_FREQ … /* Tracks if CPU frequency can be updated anymore */ static bool no_cpufreq_access; /* * DRAM configurations to calculate refresh counter for changing * frequency of memory. */ struct dram_conf { … }; /* DRAM configuration (DMC0 and DMC1) */ static struct dram_conf s5pv210_dram_conf[2]; enum perf_level { … }; enum s5pv210_mem_type { … }; enum s5pv210_dmc_port { … }; static struct cpufreq_frequency_table s5pv210_freq_table[] = …; static struct regulator *arm_regulator; static struct regulator *int_regulator; struct s5pv210_dvs_conf { … }; static const int arm_volt_max = …; static const int int_volt_max = …; static struct s5pv210_dvs_conf dvs_conf[] = …; static u32 clkdiv_val[5][11] = …; /* * This function set DRAM refresh counter * according to operating frequency of DRAM * ch: DMC port number 0 or 1 * freq: Operating frequency of DRAM(KHz) */ static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq) { … } static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) { … } static int check_mem_type(void __iomem *dmc_reg) { … } static int s5pv210_cpu_init(struct cpufreq_policy *policy) { … } static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this, unsigned long event, void *ptr) { … } static struct cpufreq_driver s5pv210_driver = …; static struct notifier_block s5pv210_cpufreq_reboot_notifier = …; static int s5pv210_cpufreq_probe(struct platform_device *pdev) { … } static struct platform_driver s5pv210_cpufreq_platdrv = …; builtin_platform_driver(…) …;
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