/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 Traphandler * Copyright (C) 2014 Free Electrons * Copyright (C) 2014 Atmel * * Author: Jean-Jacques Hiblot <[email protected]> * Author: Boris BREZILLON <[email protected]> */ #ifndef DRM_ATMEL_HLCDC_H #define DRM_ATMEL_HLCDC_H #include <linux/regmap.h> #include <drm/drm_plane.h> /* LCD controller common registers */ #define ATMEL_HLCDC_LAYER_CHER … #define ATMEL_HLCDC_LAYER_CHDR … #define ATMEL_HLCDC_LAYER_CHSR … #define ATMEL_HLCDC_LAYER_EN … #define ATMEL_HLCDC_LAYER_UPDATE … #define ATMEL_HLCDC_LAYER_A2Q … #define ATMEL_HLCDC_LAYER_RST … #define ATMEL_HLCDC_LAYER_IER … #define ATMEL_HLCDC_LAYER_IDR … #define ATMEL_HLCDC_LAYER_IMR … #define ATMEL_HLCDC_LAYER_ISR … #define ATMEL_HLCDC_LAYER_DFETCH … #define ATMEL_HLCDC_LAYER_LFETCH … #define ATMEL_HLCDC_LAYER_DMA_IRQ(p) … #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) … #define ATMEL_HLCDC_LAYER_ADD_IRQ(p) … #define ATMEL_HLCDC_LAYER_DONE_IRQ(p) … #define ATMEL_HLCDC_LAYER_OVR_IRQ(p) … #define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) … #define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) … #define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) … #define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) … #define ATMEL_HLCDC_LAYER_DMA_CFG … #define ATMEL_HLCDC_LAYER_DMA_SIF … #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK … #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE … #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 … #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 … #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 … #define ATMEL_HLCDC_LAYER_DMA_DLBO … #define ATMEL_HLCDC_LAYER_DMA_ROTDIS … #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS … #define ATMEL_HLCDC_LAYER_FORMAT_CFG … #define ATMEL_HLCDC_LAYER_RGB … #define ATMEL_HLCDC_LAYER_CLUT … #define ATMEL_HLCDC_LAYER_YUV … #define ATMEL_HLCDC_RGB_MODE(m) … #define ATMEL_HLCDC_CLUT_MODE(m) … #define ATMEL_HLCDC_YUV_MODE(m) … #define ATMEL_HLCDC_YUV422ROT … #define ATMEL_HLCDC_YUV422SWP … #define ATMEL_HLCDC_DSCALEOPT … #define ATMEL_HLCDC_C1_MODE … #define ATMEL_HLCDC_C2_MODE … #define ATMEL_HLCDC_C4_MODE … #define ATMEL_HLCDC_C8_MODE … #define ATMEL_HLCDC_XRGB4444_MODE … #define ATMEL_HLCDC_ARGB4444_MODE … #define ATMEL_HLCDC_RGBA4444_MODE … #define ATMEL_HLCDC_RGB565_MODE … #define ATMEL_HLCDC_ARGB1555_MODE … #define ATMEL_HLCDC_XRGB8888_MODE … #define ATMEL_HLCDC_RGB888_MODE … #define ATMEL_HLCDC_ARGB8888_MODE … #define ATMEL_HLCDC_RGBA8888_MODE … #define ATMEL_HLCDC_AYUV_MODE … #define ATMEL_HLCDC_YUYV_MODE … #define ATMEL_HLCDC_UYVY_MODE … #define ATMEL_HLCDC_YVYU_MODE … #define ATMEL_HLCDC_VYUY_MODE … #define ATMEL_HLCDC_NV61_MODE … #define ATMEL_HLCDC_YUV422_MODE … #define ATMEL_HLCDC_NV21_MODE … #define ATMEL_HLCDC_YUV420_MODE … #define ATMEL_HLCDC_LAYER_POS(x, y) … #define ATMEL_HLCDC_LAYER_SIZE(w, h) … #define ATMEL_HLCDC_LAYER_CRKEY … #define ATMEL_HLCDC_LAYER_INV … #define ATMEL_HLCDC_LAYER_ITER2BL … #define ATMEL_HLCDC_LAYER_ITER … #define ATMEL_HLCDC_LAYER_REVALPHA … #define ATMEL_HLCDC_LAYER_GAEN … #define ATMEL_HLCDC_LAYER_LAEN … #define ATMEL_HLCDC_LAYER_OVR … #define ATMEL_HLCDC_LAYER_DMA … #define ATMEL_HLCDC_LAYER_REP … #define ATMEL_HLCDC_LAYER_DSTKEY … #define ATMEL_HLCDC_LAYER_DISCEN … #define ATMEL_HLCDC_LAYER_GA_SHIFT … #define ATMEL_HLCDC_LAYER_GA_MASK … #define ATMEL_HLCDC_LAYER_GA(x) … #define ATMEL_HLCDC_LAYER_DISC_POS(x, y) … #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) … #define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) … #define ATMEL_HLCDC_LAYER_SCALER_ENABLE … #define ATMEL_HLCDC_LAYER_MAX_PLANES … #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED … #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED … #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE … #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN … #define ATMEL_HLCDC_CLUT_SIZE … #define ATMEL_HLCDC_MAX_LAYERS … /* XLCDC controller specific registers */ #define ATMEL_XLCDC_LAYER_ENR … #define ATMEL_XLCDC_LAYER_EN … #define ATMEL_XLCDC_LAYER_IER … #define ATMEL_XLCDC_LAYER_IDR … #define ATMEL_XLCDC_LAYER_ISR … #define ATMEL_XLCDC_LAYER_OVR_IRQ(p) … #define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) … #define ATMEL_XLCDC_LAYER_DMA_CFG … #define ATMEL_XLCDC_LAYER_DMA … #define ATMEL_XLCDC_LAYER_REP … #define ATMEL_XLCDC_LAYER_DISCEN … #define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS … #define ATMEL_XLCDC_LAYER_SFACTA_ONE … #define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS … #define ATMEL_XLCDC_LAYER_DFACTA_ONE … #define ATMEL_XLCDC_LAYER_A0_SHIFT … #define ATMEL_XLCDC_LAYER_A0(x) … #define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE … #define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE … #define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE … #define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE … #define ATMEL_XLCDC_LAYER_VXSYCFG_ONE … #define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE … #define ATMEL_XLCDC_LAYER_VXSCCFG_ONE … #define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE … #define ATMEL_XLCDC_LAYER_HXSYCFG_ONE … #define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE … #define ATMEL_XLCDC_LAYER_HXSCCFG_ONE … #define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE … /** * Atmel HLCDC Layer registers layout structure * * Each HLCDC layer has its own register organization and a given register * can be placed differently on 2 different layers depending on its * capabilities. * This structure stores common registers layout for a given layer and is * used by HLCDC layer code to choose the appropriate register to write to * or to read from. * * For all fields, a value of zero means "unsupported". * * See Atmel's datasheet for a detailled description of these registers. * * @xstride: xstride registers * @pstride: pstride registers * @pos: position register * @size: displayed size register * @memsize: memory size register * @default_color: default color register * @chroma_key: chroma key register * @chroma_key_mask: chroma key mask register * @general_config: general layer config register * @sacler_config: scaler factors register * @phicoeffs: X/Y PHI coefficient registers * @disc_pos: discard area position register * @disc_size: discard area size register * @csc: color space conversion register * @vxs_config: vertical scalar filter taps control register * @hxs_config: horizontal scalar filter taps control register */ struct atmel_hlcdc_layer_cfg_layout { … }; /** * Atmel HLCDC DMA descriptor structure * * This structure is used by the HLCDC DMA engine to schedule a DMA transfer. * * The structure fields must remain in this specific order, because they're * used by the HLCDC DMA engine, which expect them in this order. * HLCDC DMA descriptors must be aligned on 64 bits. * * @addr: buffer DMA address * @ctrl: DMA transfer options * @next: next DMA descriptor to fetch * @self: descriptor DMA address */ struct atmel_hlcdc_dma_channel_dscr { … } __aligned(…); /** * Atmel HLCDC layer types */ enum atmel_hlcdc_layer_type { … }; /** * Atmel HLCDC Supported formats structure * * This structure list all the formats supported by a given layer. * * @nformats: number of supported formats * @formats: supported formats */ struct atmel_hlcdc_formats { … }; /** * Atmel HLCDC Layer description structure * * This structure describes the capabilities provided by a given layer. * * @name: layer name * @type: layer type * @id: layer id * @regs_offset: offset of the layer registers from the HLCDC registers base * @cfgs_offset: CFGX registers offset from the layer registers base * @formats: supported formats * @layout: config registers layout * @max_width: maximum width supported by this layer (0 means unlimited) * @max_height: maximum height supported by this layer (0 means unlimited) */ struct atmel_hlcdc_layer_desc { … }; /** * Atmel HLCDC Layer. * * A layer can be a DRM plane of a post processing layer used to render * HLCDC composition into memory. * * @desc: layer description * @regmap: pointer to the HLCDC regmap */ struct atmel_hlcdc_layer { … }; /** * Atmel HLCDC Plane. * * @base: base DRM plane structure * @layer: HLCDC layer structure * @properties: pointer to the property definitions structure */ struct atmel_hlcdc_plane { … }; static inline struct atmel_hlcdc_plane * drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p) { … } static inline struct atmel_hlcdc_plane * atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) { … } /** * struct atmel_hlcdc_dc - Atmel HLCDC Display Controller. * @desc: HLCDC Display Controller description * @dscrpool: DMA coherent pool used to allocate DMA descriptors * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device * @crtc: CRTC provided by the display controller * @layers: active HLCDC layers * @suspend: used to store the HLCDC state when entering suspend * @suspend.imr: used to read/write LCDC Interrupt Mask Register * @suspend.state: Atomic commit structure */ struct atmel_hlcdc_dc { … }; struct atmel_hlcdc_plane_state; /** * struct atmel_lcdc_dc_ops - describes atmel_lcdc ops group * to differentiate HLCDC and XLCDC IP code support * @plane_setup_scaler: update the vertical and horizontal scaling factors * @update_lcdc_buffers: update the each LCDC layers DMA registers * @lcdc_atomic_disable: disable LCDC interrupts and layers * @lcdc_update_general_settings: update each LCDC layers general * configuration register * @lcdc_atomic_update: enable the LCDC layers and interrupts * @lcdc_csc_init: update the color space conversion co-efficient of * High-end overlay register * @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC layer */ struct atmel_lcdc_dc_ops { … }; extern const struct atmel_lcdc_dc_ops atmel_hlcdc_ops; extern const struct atmel_lcdc_dc_ops atmel_xlcdc_ops; /** * Atmel HLCDC Display Controller description structure. * * This structure describes the HLCDC IP capabilities and depends on the * HLCDC IP version (or Atmel SoC family). * * @min_width: minimum width supported by the Display Controller * @min_height: minimum height supported by the Display Controller * @max_width: maximum width supported by the Display Controller * @max_height: maximum height supported by the Display Controller * @max_spw: maximum vertical/horizontal pulse width * @max_vpw: maximum vertical back/front porch width * @max_hpw: maximum horizontal back/front porch width * @conflicting_output_formats: true if RGBXXX output formats conflict with * each other. * @fixed_clksrc: true if clock source is fixed * @is_xlcdc: true if XLCDC IP is supported * @layers: a layer description table describing available layers * @nlayers: layer description table size * @ops: atmel lcdc dc ops */ struct atmel_hlcdc_dc_desc { … }; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats; static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer, unsigned int reg, u32 val) { … } static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer, unsigned int reg) { … } static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer, unsigned int cfgid, u32 val) { … } static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer, unsigned int cfgid) { … } static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer, unsigned int c, u32 val) { … } static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer, const struct atmel_hlcdc_layer_desc *desc, struct regmap *regmap) { … } enum drm_mode_status atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, const struct drm_display_mode *mode); int atmel_hlcdc_create_planes(struct drm_device *dev); void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane); int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state); int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state); void atmel_hlcdc_crtc_irq(struct drm_crtc *c); int atmel_hlcdc_crtc_create(struct drm_device *dev); int atmel_hlcdc_create_outputs(struct drm_device *dev); int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder); #endif /* DRM_ATMEL_HLCDC_H */
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