linux/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * DMM IOMMU driver support functions for TI OMAP processors.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
 * Author: Rob Clark <[email protected]>
 *         Andy Gross <[email protected]>
 */

#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h> /* platform_device() */
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/vmalloc.h>
#include <linux/wait.h>

#include "omap_dmm_tiler.h"
#include "omap_dmm_priv.h"

#define DMM_DRIVER_NAME

/* mappings for associating views to luts */
static struct tcm *containers[TILFMT_NFORMATS];
static struct dmm *omap_dmm;

#if defined(CONFIG_OF)
static const struct of_device_id dmm_of_match[];
#endif

/* global spinlock for protecting lists */
static DEFINE_SPINLOCK(list_lock);

/* Geometry table */
#define GEOM(xshift, yshift, bytes_per_pixel)

static const struct {} geom[TILFMT_NFORMATS] =;


/* lookup table for registers w/ per-engine instances */
static const u32 reg[][4] =;

static int dmm_dma_copy(struct dmm *dmm, dma_addr_t src, dma_addr_t dst)
{}

static u32 dmm_read_wa(struct dmm *dmm, u32 reg)
{}

static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg)
{}

static u32 dmm_read(struct dmm *dmm, u32 reg)
{}

static void dmm_write(struct dmm *dmm, u32 val, u32 reg)
{}

static int dmm_workaround_init(struct dmm *dmm)
{}

static void dmm_workaround_uninit(struct dmm *dmm)
{}

/* simple allocator to grab next 16 byte aligned memory from txn */
static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
{}

/* check status and spin until wait_mask comes true */
static int wait_status(struct refill_engine *engine, u32 wait_mask)
{}

static void release_engine(struct refill_engine *engine)
{}

static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
{}

/*
 * Get a handle for a DMM transaction
 */
static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
{}

/*
 * Add region to DMM transaction.  If pages or pages[i] is NULL, then the
 * corresponding slot is cleared (ie. dummy_pa is programmed)
 */
static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
		struct page **pages, u32 npages, u32 roll)
{}

/*
 * Commit the DMM transaction.
 */
static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
{}

/*
 * DMM programming
 */
static int fill(struct tcm_area *area, struct page **pages,
		u32 npages, u32 roll, bool wait)
{}

/*
 * Pin/unpin
 */

/* note: slots for which pages[i] == NULL are filled w/ dummy page
 */
int tiler_pin(struct tiler_block *block, struct page **pages,
		u32 npages, u32 roll, bool wait)
{}

int tiler_unpin(struct tiler_block *block)
{}

/*
 * Reserve/release
 */
struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,
		u16 h, u16 align)
{}

struct tiler_block *tiler_reserve_1d(size_t size)
{}

/* note: if you have pin'd pages, you should have already unpin'd first! */
int tiler_release(struct tiler_block *block)
{}

/*
 * Utils
 */

/* calculate the tiler space address of a pixel in a view orientation...
 * below description copied from the display subsystem section of TRM:
 *
 * When the TILER is addressed, the bits:
 *   [28:27] = 0x0 for 8-bit tiled
 *             0x1 for 16-bit tiled
 *             0x2 for 32-bit tiled
 *             0x3 for page mode
 *   [31:29] = 0x0 for 0-degree view
 *             0x1 for 180-degree view + mirroring
 *             0x2 for 0-degree view + mirroring
 *             0x3 for 180-degree view
 *             0x4 for 270-degree view + mirroring
 *             0x5 for 270-degree view
 *             0x6 for 90-degree view
 *             0x7 for 90-degree view + mirroring
 * Otherwise the bits indicated the corresponding bit address to access
 * the SDRAM.
 */
static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
{}

dma_addr_t tiler_ssptr(struct tiler_block *block)
{}

dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,
		u32 x, u32 y)
{}

void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h)
{}

u32 tiler_stride(enum tiler_fmt fmt, u32 orient)
{}

size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h)
{}

size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h)
{}

u32 tiler_get_cpu_cache_flags(void)
{}

bool dmm_is_available(void)
{}

static void omap_dmm_remove(struct platform_device *dev)
{}

static int omap_dmm_probe(struct platform_device *dev)
{}

/*
 * debugfs support
 */

#ifdef CONFIG_DEBUG_FS

static const char *alphabet =;
static const char *special =;

static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
							char c, bool ovw)
{}

static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
									char c)
{}

static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
{}

static int map_width(int xdiv, int x0, int x1)
{}

static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
{}

static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
							struct tcm_area *a)
{}

static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
							struct tcm_area *a)
{}

int tiler_map_show(struct seq_file *s, void *arg)
{}
#endif

#ifdef CONFIG_PM_SLEEP
static int omap_dmm_resume(struct device *dev)
{}
#endif

static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume);

#if defined(CONFIG_OF)
static const struct dmm_platform_data dmm_omap4_platform_data =;

static const struct dmm_platform_data dmm_omap5_platform_data =;

static const struct of_device_id dmm_of_match[] =;
#endif

struct platform_driver omap_dmm_driver =;

MODULE_LICENSE();
MODULE_AUTHOR();
MODULE_DESCRIPTION();