// SPDX-License-Identifier: GPL-2.0+ /* * Marvell Armada AP CPU Clock Controller * * Copyright (C) 2018 Marvell * * Omri Itach <[email protected]> * Gregory Clement <[email protected]> */ #define pr_fmt(fmt) … #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include "armada_ap_cp_helper.h" #define AP806_CPU_CLUSTER0 … #define AP806_CPU_CLUSTER1 … #define AP806_CPUS_PER_CLUSTER … #define APN806_CPU1_MASK … #define APN806_CLUSTER_NUM_OFFSET … #define APN806_CLUSTER_NUM_MASK … #define APN806_MAX_DIVIDER … /* * struct cpu_dfs_regs: CPU DFS register mapping * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency * @force_reg: request to force new ratio regardless of relation to other clocks * @ratio_reg: central request to switch ratios */ struct cpu_dfs_regs { … }; /* AP806 CPU DFS register mapping*/ #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET … #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET … #define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET … #define AP806_CA72MP2_0_PLL_SR_REG_OFFSET … #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET … #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET … #define AP806_PLL_CR_CPU_CLK_DIV_RATIO … #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK … #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET … #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK … #define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET … #define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET … #define AP806_CA72MP2_0_PLL_RATIO_STATE … #define STATUS_POLL_PERIOD_US … #define STATUS_POLL_TIMEOUT_US … #define to_ap_cpu_clk(_hw) … static const struct cpu_dfs_regs ap806_dfs_regs = …; /* AP807 CPU DFS register mapping */ #define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET … #define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET … #define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET … #define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET … #define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET … #define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK … #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET … #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK … #define AP807_PLL_CR_CPU_CLK_DIV_RATIO … #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET … #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK … #define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET … #define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET … #define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET … static const struct cpu_dfs_regs ap807_dfs_regs = …; /* * struct ap806_clk: CPU cluster clock controller instance * @cluster: Cluster clock controller index * @clk_name: Cluster clock controller name * @dev : Cluster clock device * @hw: HW specific structure of Cluster clock controller * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register) */ struct ap_cpu_clk { … }; static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static const struct clk_ops ap_cpu_clk_ops = …; static int ap_cpu_clock_probe(struct platform_device *pdev) { … } static const struct of_device_id ap_cpu_clock_of_match[] = …; static struct platform_driver ap_cpu_clock_driver = …; builtin_platform_driver(…) …;
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