/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) Meta Platforms, Inc. and affiliates. */ #ifndef _FBNIC_CSR_H_ #define _FBNIC_CSR_H_ #include <linux/bitops.h> #define CSR_BIT(nr) … #define CSR_GENMASK(h, l) … #define DESC_BIT(nr) … #define DESC_GENMASK(h, l) … /* Defines the minimum firmware version required by the driver */ #define MIN_FW_MAJOR_VERSION … #define MIN_FW_MINOR_VERSION … #define MIN_FW_BUILD_VERSION … #define MIN_FW_VERSION_CODE … #define PCI_DEVICE_ID_META_FBNIC_ASIC … #define FBNIC_CLOCK_FREQ … /* Transmit Work Descriptor Format */ /* Length, Type, Offset Masks and Shifts */ #define FBNIC_TWD_L2_HLEN_MASK … #define FBNIC_TWD_L3_TYPE_MASK … enum { … }; #define FBNIC_TWD_L3_OHLEN_MASK … #define FBNIC_TWD_L3_IHLEN_MASK … enum { … }; #define FBNIC_TWD_CSUM_OFFSET_MASK … #define FBNIC_TWD_L4_HLEN_MASK … /* Flags and Type */ #define FBNIC_TWD_L4_TYPE_MASK … #define FBNIC_TWD_FLAG_REQ_TS … #define FBNIC_TWD_FLAG_REQ_LSO … #define FBNIC_TWD_FLAG_REQ_CSO … #define FBNIC_TWD_FLAG_REQ_COMPLETION … #define FBNIC_TWD_FLAG_DEST_MAC … #define FBNIC_TWD_FLAG_DEST_BMC … #define FBNIC_TWD_FLAG_DEST_FW … #define FBNIC_TWD_TYPE_MASK … enum { … }; /* MSS and Completion Req */ #define FBNIC_TWD_MSS_MASK … #define FBNIC_TWD_TS_MASK … #define FBNIC_TWD_ADDR_MASK … #define FBNIC_TWD_LEN_MASK … /* Tx Completion Descriptor Format */ #define FBNIC_TCD_TYPE0_HEAD0_MASK … #define FBNIC_TCD_TYPE0_HEAD1_MASK … #define FBNIC_TCD_TYPE1_TS_MASK … #define FBNIC_TCD_STATUS_MASK … #define FBNIC_TCD_STATUS_TS_INVALID … #define FBNIC_TCD_STATUS_ILLEGAL_TS_REQ … #define FBNIC_TCD_TWQ1 … #define FBNIC_TCD_TYPE_MASK … enum { … }; #define FBNIC_TCD_DONE … /* Rx Buffer Descriptor Format * * The layout of this can vary depending on the page size of the system. * * If the page size is 4K then the layout will simply consist of ID for * the 16 most significant bits, and the lower 46 are essentially the page * address with the lowest 12 bits being reserved 0 due to the fact that * a page will be aligned. * * If the page size is larger than 4K then the lower n bits of the ID and * page address will be reserved for the fragment ID. This fragment will * be 4K in size and will be used to index both the DMA address and the ID * by the same amount. */ #define FBNIC_BD_DESC_ADDR_MASK … #define FBNIC_BD_DESC_ID_MASK … #define FBNIC_BD_FRAG_SIZE … #define FBNIC_BD_FRAG_COUNT … #define FBNIC_BD_FRAG_ADDR_MASK … #define FBNIC_BD_FRAG_ID_MASK … #define FBNIC_BD_PAGE_ADDR_MASK … #define FBNIC_BD_PAGE_ID_MASK … /* Rx Completion Queue Descriptors */ #define FBNIC_RCD_TYPE_MASK … enum { … }; #define FBNIC_RCD_DONE … /* Address/Length Completion Descriptors */ #define FBNIC_RCD_AL_BUFF_ID_MASK … #define FBNIC_RCD_AL_BUFF_FRAG_MASK … #define FBNIC_RCD_AL_BUFF_PAGE_MASK … #define FBNIC_RCD_AL_BUFF_LEN_MASK … #define FBNIC_RCD_AL_BUFF_OFF_MASK … #define FBNIC_RCD_AL_PAGE_FIN … /* Header AL specific values */ #define FBNIC_RCD_HDR_AL_OVERFLOW … #define FBNIC_RCD_HDR_AL_DMA_HINT_MASK … enum { … }; /* Optional Metadata Completion Descriptors */ #define FBNIC_RCD_OPT_META_TS_MASK … #define FBNIC_RCD_OPT_META_ACTION_MASK … #define FBNIC_RCD_OPT_META_ACTION … #define FBNIC_RCD_OPT_META_TS … #define FBNIC_RCD_OPT_META_TYPE_MASK … /* Metadata Completion Descriptors */ #define FBNIC_RCD_META_RSS_HASH_MASK … #define FBNIC_RCD_META_L2_CSUM_MASK … #define FBNIC_RCD_META_L3_TYPE_MASK … enum { … }; #define FBNIC_RCD_META_L4_TYPE_MASK … enum { … }; #define FBNIC_RCD_META_L4_CSUM_UNNECESSARY … #define FBNIC_RCD_META_ERR_MAC_EOP … #define FBNIC_RCD_META_ERR_TRUNCATED_FRAME … #define FBNIC_RCD_META_ERR_PARSER … #define FBNIC_RCD_META_UNCORRECTABLE_ERR_MASK … #define FBNIC_RCD_META_ECN … /* Register Definitions * * The registers are laid as indexes into an le32 array. As such the actual * address is 4 times the index value. Below each register is defined as 3 * fields, name, index, and Address. * * Name Index Address *************************************************************************/ /* Interrupt Registers */ #define FBNIC_CSR_START_INTR … #define FBNIC_INTR_STATUS(n) … #define FBNIC_INTR_STATUS_CNT … #define FBNIC_INTR_MASK(n) … #define FBNIC_INTR_MASK_CNT … #define FBNIC_INTR_SET(n) … #define FBNIC_INTR_SET_CNT … #define FBNIC_INTR_CLEAR(n) … #define FBNIC_INTR_CLEAR_CNT … #define FBNIC_INTR_SW_STATUS(n) … #define FBNIC_INTR_SW_STATUS_CNT … #define FBNIC_INTR_SW_AC_MODE(n) … #define FBNIC_INTR_SW_AC_MODE_CNT … #define FBNIC_INTR_MASK_SET(n) … #define FBNIC_INTR_MASK_SET_CNT … #define FBNIC_INTR_MASK_CLEAR(n) … #define FBNIC_INTR_MASK_CLEAR_CNT … #define FBNIC_MAX_MSIX_VECS … #define FBNIC_INTR_MSIX_CTRL(n) … #define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK … #define FBNIC_INTR_MSIX_CTRL_ENABLE … enum { … }; #define FBNIC_CSR_END_INTR … /* Interrupt MSIX Registers */ #define FBNIC_CSR_START_INTR_CQ … #define FBNIC_INTR_CQ_REARM(n) … #define FBNIC_INTR_CQ_REARM_CNT … #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT … #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT_UPD_EN … #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT … #define FBNIC_INTR_CQ_REARM_TCQ_TIMEOUT_UPD_EN … #define FBNIC_INTR_CQ_REARM_INTR_RELOAD … #define FBNIC_INTR_CQ_REARM_INTR_UNMASK … #define FBNIC_INTR_RCQ_TIMEOUT(n) … #define FBNIC_INTR_RCQ_TIMEOUT_CNT … #define FBNIC_INTR_TCQ_TIMEOUT(n) … #define FBNIC_INTR_TCQ_TIMEOUT_CNT … #define FBNIC_CSR_END_INTR_CQ … /* Global QM Tx registers */ #define FBNIC_CSR_START_QM_TX … #define FBNIC_QM_TWQ_IDLE(n) … #define FBNIC_QM_TWQ_IDLE_CNT … #define FBNIC_QM_TWQ_DEFAULT_META_L … #define FBNIC_QM_TWQ_DEFAULT_META_H … #define FBNIC_QM_TQS_CTL0 … #define FBNIC_QM_TQS_CTL0_LSO_TS_MASK … enum { … }; #define FBNIC_QM_TQS_CTL0_PREFETCH_THRESH … enum { … }; #define FBNIC_QM_TQS_CTL1 … #define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS … #define FBNIC_QM_TQS_CTL1_BULK_MAX_CREDITS … #define FBNIC_QM_TQS_MTU_CTL0 … #define FBNIC_QM_TQS_MTU_CTL1 … #define FBNIC_QM_TQS_MTU_CTL1_BULK … #define FBNIC_QM_TCQ_IDLE(n) … #define FBNIC_QM_TCQ_IDLE_CNT … #define FBNIC_QM_TCQ_CTL0 … #define FBNIC_QM_TCQ_CTL0_COAL_WAIT … #define FBNIC_QM_TCQ_CTL0_TICK_CYCLES … #define FBNIC_QM_TQS_IDLE(n) … #define FBNIC_QM_TQS_IDLE_CNT … #define FBNIC_QM_TQS_EDT_TS_RANGE … #define FBNIC_QM_TDE_IDLE(n) … #define FBNIC_QM_TDE_IDLE_CNT … #define FBNIC_QM_TNI_TDF_CTL … #define FBNIC_QM_TNI_TDF_CTL_MRRS … #define FBNIC_QM_TNI_TDF_CTL_CLS … #define FBNIC_QM_TNI_TDF_CTL_MAX_OT … #define FBNIC_QM_TNI_TDF_CTL_MAX_OB … #define FBNIC_QM_TNI_TDE_CTL … #define FBNIC_QM_TNI_TDE_CTL_MRRS … #define FBNIC_QM_TNI_TDE_CTL_CLS … #define FBNIC_QM_TNI_TDE_CTL_MAX_OT … #define FBNIC_QM_TNI_TDE_CTL_MAX_OB … #define FBNIC_QM_TNI_TDE_CTL_MRRS_1K … #define FBNIC_QM_TNI_TCM_CTL … #define FBNIC_QM_TNI_TCM_CTL_MPS … #define FBNIC_QM_TNI_TCM_CTL_CLS … #define FBNIC_QM_TNI_TCM_CTL_MAX_OT … #define FBNIC_QM_TNI_TCM_CTL_MAX_OB … #define FBNIC_CSR_END_QM_TX … /* Global QM Rx registers */ #define FBNIC_CSR_START_QM_RX … #define FBNIC_QM_RCQ_IDLE(n) … #define FBNIC_QM_RCQ_IDLE_CNT … #define FBNIC_QM_RCQ_CTL0 … #define FBNIC_QM_RCQ_CTL0_COAL_WAIT … #define FBNIC_QM_RCQ_CTL0_TICK_CYCLES … #define FBNIC_QM_HPQ_IDLE(n) … #define FBNIC_QM_HPQ_IDLE_CNT … #define FBNIC_QM_PPQ_IDLE(n) … #define FBNIC_QM_PPQ_IDLE_CNT … #define FBNIC_QM_RNI_RBP_CTL … #define FBNIC_QM_RNI_RBP_CTL_MRRS … #define FBNIC_QM_RNI_RBP_CTL_CLS … #define FBNIC_QM_RNI_RBP_CTL_MAX_OT … #define FBNIC_QM_RNI_RBP_CTL_MAX_OB … #define FBNIC_QM_RNI_RDE_CTL … #define FBNIC_QM_RNI_RDE_CTL_MPS … #define FBNIC_QM_RNI_RDE_CTL_CLS … #define FBNIC_QM_RNI_RDE_CTL_MAX_OT … #define FBNIC_QM_RNI_RDE_CTL_MAX_OB … #define FBNIC_QM_RNI_RCM_CTL … #define FBNIC_QM_RNI_RCM_CTL_MPS … #define FBNIC_QM_RNI_RCM_CTL_CLS … #define FBNIC_QM_RNI_RCM_CTL_MAX_OT … #define FBNIC_QM_RNI_RCM_CTL_MAX_OB … #define FBNIC_CSR_END_QM_RX … /* TCE registers */ #define FBNIC_CSR_START_TCE … #define FBNIC_TCE_REG_BASE … #define FBNIC_TCE_LSO_CTRL … #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST … #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_MID … #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_END … #define FBNIC_TCE_LSO_CTRL_IPID_MODE_INC … #define FBNIC_TCE_CSO_CTRL … #define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM … #define FBNIC_TCE_TXB_CTRL … #define FBNIC_TCE_TXB_CTRL_LOAD … #define FBNIC_TCE_TXB_CTRL_TCAM_ENABLE … #define FBNIC_TCE_TXB_CTRL_DISABLE … #define FBNIC_TCE_TXB_ENQ_WRR_CTRL … #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 … #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT1 … #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT2 … #define FBNIC_TCE_TXB_TEI_Q0_CTRL … #define FBNIC_TCE_TXB_TEI_Q1_CTRL … #define FBNIC_TCE_TXB_MC_Q_CTRL … #define FBNIC_TCE_TXB_RX_TEI_Q_CTRL … #define FBNIC_TCE_TXB_RX_BMC_Q_CTRL … #define FBNIC_TCE_TXB_Q_CTRL_START … #define FBNIC_TCE_TXB_Q_CTRL_SIZE … #define FBNIC_TCE_TXB_TEI_DWRR_CTRL … #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 … #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM1 … #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL … #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 … #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM1 … #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM2 … #define FBNIC_TCE_TXB_CLDR_CFG … #define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_CNT … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_1 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_2 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_3 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_0 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_1 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_2 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_1_3 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_0 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_1 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_2 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_2_3 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_0 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_1 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_2 … #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_3_3 … #define FBNIC_TCE_BMC_MAX_PKTSZ … #define FBNIC_TCE_BMC_MAX_PKTSZ_TX … #define FBNIC_TCE_BMC_MAX_PKTSZ_RX … #define FBNIC_TCE_MC_MAX_PKTSZ … #define FBNIC_TCE_MC_MAX_PKTSZ_TMI … #define FBNIC_TCE_SOP_PROT_CTRL … #define FBNIC_TCE_SOP_PROT_CTRL_TBI … #define FBNIC_TCE_SOP_PROT_CTRL_TTI_FRM … #define FBNIC_TCE_SOP_PROT_CTRL_TTI_CM … #define FBNIC_TCE_DROP_CTRL … #define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN … #define FBNIC_TCE_DROP_CTRL_TTI_FRM_DROP_EN … #define FBNIC_TCE_DROP_CTRL_TTI_TBI_DROP_EN … #define FBNIC_TCE_TXB_TX_BMC_Q_CTRL … #define FBNIC_TCE_TXB_BMC_DWRR_CTRL … #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 … #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM1 … #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT … #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_EXT … #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT … #define FBNIC_CSR_END_TCE … /* TMI registers */ #define FBNIC_CSR_START_TMI … #define FBNIC_TMI_SOP_PROT_CTRL … #define FBNIC_TMI_DROP_CTRL … #define FBNIC_TMI_DROP_CTRL_EN … #define FBNIC_CSR_END_TMI … /* Rx Buffer Registers */ #define FBNIC_CSR_START_RXB … enum { … }; #define FBNIC_RXB_CT_SIZE(n) … #define FBNIC_RXB_CT_SIZE_CNT … #define FBNIC_RXB_CT_SIZE_HEADER … #define FBNIC_RXB_CT_SIZE_PAYLOAD … #define FBNIC_RXB_CT_SIZE_ENABLE … #define FBNIC_RXB_PAUSE_DROP_CTRL … #define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE … #define FBNIC_RXB_PAUSE_DROP_CTRL_PAUSE_ENABLE … #define FBNIC_RXB_PAUSE_DROP_CTRL_ECN_ENABLE … #define FBNIC_RXB_PAUSE_DROP_CTRL_PS_ENABLE … #define FBNIC_RXB_PAUSE_THLD(n) … #define FBNIC_RXB_PAUSE_THLD_CNT … #define FBNIC_RXB_PAUSE_THLD_ON … #define FBNIC_RXB_PAUSE_THLD_OFF … #define FBNIC_RXB_DROP_THLD(n) … #define FBNIC_RXB_DROP_THLD_CNT … #define FBNIC_RXB_DROP_THLD_ON … #define FBNIC_RXB_DROP_THLD_OFF … #define FBNIC_RXB_ECN_THLD(n) … #define FBNIC_RXB_ECN_THLD_CNT … #define FBNIC_RXB_ECN_THLD_ON … #define FBNIC_RXB_ECN_THLD_OFF … #define FBNIC_RXB_PBUF_CFG(n) … #define FBNIC_RXB_PBUF_CFG_CNT … #define FBNIC_RXB_PBUF_BASE_ADDR … #define FBNIC_RXB_PBUF_SIZE … #define FBNIC_RXB_DWRR_RDE_WEIGHT0 … #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 … #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM1 … #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM2 … #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM3 … #define FBNIC_RXB_DWRR_RDE_WEIGHT1 … #define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 … #define FBNIC_RXB_DWRR_BMC_WEIGHT … #define FBNIC_RXB_CLDR_PRIO_CFG(n) … #define FBNIC_RXB_CLDR_PRIO_CFG_CNT … #define FBNIC_RXB_ENDIAN_FCS … enum { … }; #define FBNIC_RXB_PBUF_CREDIT(n) … #define FBNIC_RXB_PBUF_CREDIT_CNT … #define FBNIC_RXB_PBUF_CREDIT_MASK … #define FBNIC_RXB_INTF_CREDIT … #define FBNIC_RXB_INTF_CREDIT_MASK0 … #define FBNIC_RXB_INTF_CREDIT_MASK1 … #define FBNIC_RXB_INTF_CREDIT_MASK2 … #define FBNIC_RXB_INTF_CREDIT_MASK3 … #define FBNIC_RXB_PAUSE_EVENT_CNT(n) … #define FBNIC_RXB_DROP_FRMS_STS(n) … #define FBNIC_RXB_DROP_BYTES_STS_L(n) … #define FBNIC_RXB_DROP_BYTES_STS_H(n) … #define FBNIC_RXB_TRUN_FRMS_STS(n) … #define FBNIC_RXB_TRUN_BYTES_STS_L(n) … #define FBNIC_RXB_TRUN_BYTES_STS_H(n) … #define FBNIC_RXB_TRANS_PAUSE_STS(n) … #define FBNIC_RXB_TRANS_DROP_STS(n) … #define FBNIC_RXB_TRANS_ECN_STS(n) … enum { … }; #define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) … #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_L(n) … #define FBNIC_RXB_DRBO_BYTE_CNT_SRC_H(n) … #define FBNIC_RXB_INTF_FRM_CNT_DST(n) … #define FBNIC_RXB_INTF_BYTE_CNT_DST_L(n) … #define FBNIC_RXB_INTF_BYTE_CNT_DST_H(n) … #define FBNIC_RXB_PBUF_FRM_CNT_DST(n) … #define FBNIC_RXB_PBUF_BYTE_CNT_DST_L(n) … #define FBNIC_RXB_PBUF_BYTE_CNT_DST_H(n) … #define FBNIC_RXB_PBUF_FIFO_LEVEL(n) … #define FBNIC_RXB_INTEGRITY_ERR(n) … #define FBNIC_RXB_MAC_ERR(n) … #define FBNIC_RXB_PARSER_ERR(n) … #define FBNIC_RXB_FRM_ERR(n) … #define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT … #define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT … #define FBNIC_CSR_END_RXB … /* Rx Parser and Classifier Registers */ #define FBNIC_CSR_START_RPC … #define FBNIC_RPC_RMI_CONFIG … #define FBNIC_RPC_RMI_CONFIG_OH_BYTES … #define FBNIC_RPC_RMI_CONFIG_FCS_PRESENT … #define FBNIC_RPC_RMI_CONFIG_ENABLE … #define FBNIC_RPC_RMI_CONFIG_MTU … #define FBNIC_RPC_ACT_TBL0_DEFAULT … #define FBNIC_RPC_ACT_TBL0_DROP … #define FBNIC_RPC_ACT_TBL0_DEST_MASK … enum { … }; #define FBNIC_RPC_ACT_TBL0_DMA_HINT … #define FBNIC_RPC_ACT_TBL0_RSS_CTXT_ID … #define FBNIC_RPC_ACT_TBL1_DEFAULT … #define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK … enum { … }; #define FBNIC_RPC_RSS_KEY(n) … #define FBNIC_RPC_RSS_KEY_BIT_LEN … #define FBNIC_RPC_RSS_KEY_BYTE_LEN … #define FBNIC_RPC_RSS_KEY_DWORD_LEN … #define FBNIC_RPC_RSS_KEY_LAST_IDX … #define FBNIC_RPC_RSS_KEY_LAST_MASK … #define FBNIC_RPC_TCAM_MACDA_VALIDATE … #define FBNIC_CSR_END_RPC … /* RPC RAM Registers */ #define FBNIC_CSR_START_RPC_RAM … #define FBNIC_RPC_ACT_TBL0(n) … #define FBNIC_RPC_ACT_TBL1(n) … #define FBNIC_RPC_ACT_TBL_NUM_ENTRIES … /* TCAM Tables */ #define FBNIC_RPC_TCAM_VALIDATE … /* 64 Action TCAM Entries, 12 registers * 3 mixed, src port, dst port, 6 L4 words, and Validate */ #define FBNIC_RPC_TCAM_ACT(m, n) … #define FBNIC_RPC_TCAM_ACT_VALUE … #define FBNIC_RPC_TCAM_ACT_MASK … #define FBNIC_RPC_TCAM_MACDA(m, n) … #define FBNIC_RPC_TCAM_MACDA_VALUE … #define FBNIC_RPC_TCAM_MACDA_MASK … #define FBNIC_RPC_RSS_TBL(n, m) … #define FBNIC_RPC_RSS_TBL_COUNT … #define FBNIC_RPC_RSS_TBL_SIZE … #define FBNIC_CSR_END_RPC_RAM … /* Fab Registers */ #define FBNIC_CSR_START_FAB … #define FBNIC_FAB_AXI4_AR_SPACER_2_CFG … #define FBNIC_FAB_AXI4_AR_SPACER_MASK … #define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD … #define FBNIC_CSR_END_FAB … /* Master Registers */ #define FBNIC_CSR_START_MASTER … #define FBNIC_MASTER_SPARE_0 … #define FBNIC_CSR_END_MASTER … /* MAC MAC registers (ASIC only) */ #define FBNIC_CSR_START_MAC_MAC … #define FBNIC_MAC_COMMAND_CONFIG … #define FBNIC_MAC_COMMAND_CONFIG_RX_PAUSE_DIS … #define FBNIC_MAC_COMMAND_CONFIG_TX_PAUSE_DIS … #define FBNIC_MAC_COMMAND_CONFIG_FLT_HDL_DIS … #define FBNIC_MAC_COMMAND_CONFIG_TX_PAD_EN … #define FBNIC_MAC_COMMAND_CONFIG_LOOPBACK_EN … #define FBNIC_MAC_COMMAND_CONFIG_PROMISC_EN … #define FBNIC_MAC_COMMAND_CONFIG_RX_ENA … #define FBNIC_MAC_COMMAND_CONFIG_TX_ENA … #define FBNIC_MAC_CL01_PAUSE_QUANTA … #define FBNIC_MAC_CL01_QUANTA_THRESH … #define FBNIC_CSR_END_MAC_MAC … /* Signals from MAC, AN, PCS, and LED CSR registers (ASIC only) */ #define FBNIC_CSR_START_SIG … #define FBNIC_SIG_MAC_IN0 … #define FBNIC_SIG_MAC_IN0_RESET_FF_TX_CLK … #define FBNIC_SIG_MAC_IN0_RESET_FF_RX_CLK … #define FBNIC_SIG_MAC_IN0_RESET_TX_CLK … #define FBNIC_SIG_MAC_IN0_RESET_RX_CLK … #define FBNIC_SIG_MAC_IN0_TX_CRC … #define FBNIC_SIG_MAC_IN0_CFG_MODE128 … #define FBNIC_SIG_PCS_OUT0 … #define FBNIC_SIG_PCS_OUT0_LINK … #define FBNIC_SIG_PCS_OUT0_BLOCK_LOCK … #define FBNIC_SIG_PCS_OUT0_AMPS_LOCK … #define FBNIC_SIG_PCS_OUT1 … #define FBNIC_SIG_PCS_OUT1_FCFEC_LOCK … #define FBNIC_SIG_PCS_INTR_STS … #define FBNIC_SIG_PCS_INTR_LINK_DOWN … #define FBNIC_SIG_PCS_INTR_LINK_UP … #define FBNIC_SIG_PCS_INTR_MASK … #define FBNIC_CSR_END_SIG … #define FBNIC_CSR_START_MAC_STAT … #define FBNIC_MAC_STAT_RX_BYTE_COUNT_L … #define FBNIC_MAC_STAT_RX_BYTE_COUNT_H … #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_L … #define FBNIC_MAC_STAT_RX_ALIGN_ERROR_H … #define FBNIC_MAC_STAT_RX_TOOLONG_L … #define FBNIC_MAC_STAT_RX_TOOLONG_H … #define FBNIC_MAC_STAT_RX_RECEIVED_OK_L … #define FBNIC_MAC_STAT_RX_RECEIVED_OK_H … #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_L … #define FBNIC_MAC_STAT_RX_PACKET_BAD_FCS_H … #define FBNIC_MAC_STAT_RX_IFINERRORS_L … #define FBNIC_MAC_STAT_RX_IFINERRORS_H … #define FBNIC_MAC_STAT_RX_MULTICAST_L … #define FBNIC_MAC_STAT_RX_MULTICAST_H … #define FBNIC_MAC_STAT_RX_BROADCAST_L … #define FBNIC_MAC_STAT_RX_BROADCAST_H … #define FBNIC_MAC_STAT_TX_BYTE_COUNT_L … #define FBNIC_MAC_STAT_TX_BYTE_COUNT_H … #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_L … #define FBNIC_MAC_STAT_TX_TRANSMITTED_OK_H … #define FBNIC_MAC_STAT_TX_IFOUTERRORS_L … #define FBNIC_MAC_STAT_TX_IFOUTERRORS_H … #define FBNIC_MAC_STAT_TX_MULTICAST_L … #define FBNIC_MAC_STAT_TX_MULTICAST_H … #define FBNIC_MAC_STAT_TX_BROADCAST_L … #define FBNIC_MAC_STAT_TX_BROADCAST_H … /* PUL User Registers */ #define FBNIC_CSR_START_PUL_USER … #define FBNIC_PUL_OB_TLP_HDR_AW_CFG … #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME … #define FBNIC_PUL_OB_TLP_HDR_AR_CFG … #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME … #define FBNIC_CSR_END_PUL_USER … /* Queue Registers * * The queue register offsets are specific for a given queue grouping. So to * find the actual register offset it is necessary to combine FBNIC_QUEUE(n) * with the register to get the actual register offset like so: * FBNIC_QUEUE_TWQ0_CTL(n) == FBNIC_QUEUE(n) + FBNIC_QUEUE_TWQ0_CTL */ #define FBNIC_CSR_START_QUEUE … #define FBNIC_QUEUE_STRIDE … #define FBNIC_QUEUE(n) … #define FBNIC_QUEUE_TWQ0_CTL … #define FBNIC_QUEUE_TWQ1_CTL … #define FBNIC_QUEUE_TWQ_CTL_RESET … #define FBNIC_QUEUE_TWQ_CTL_ENABLE … #define FBNIC_QUEUE_TWQ0_TAIL … #define FBNIC_QUEUE_TWQ1_TAIL … #define FBNIC_QUEUE_TWQ0_SIZE … #define FBNIC_QUEUE_TWQ1_SIZE … #define FBNIC_QUEUE_TWQ_SIZE_MASK … #define FBNIC_QUEUE_TWQ0_BAL … #define FBNIC_QUEUE_BAL_MASK … #define FBNIC_QUEUE_TWQ0_BAH … #define FBNIC_QUEUE_TWQ1_BAL … #define FBNIC_QUEUE_TWQ1_BAH … /* Tx Completion Queue Registers */ #define FBNIC_QUEUE_TCQ_CTL … #define FBNIC_QUEUE_TCQ_CTL_RESET … #define FBNIC_QUEUE_TCQ_CTL_ENABLE … #define FBNIC_QUEUE_TCQ_HEAD … #define FBNIC_QUEUE_TCQ_SIZE … #define FBNIC_QUEUE_TCQ_SIZE_MASK … #define FBNIC_QUEUE_TCQ_BAL … #define FBNIC_QUEUE_TCQ_BAH … /* Tx Interrupt Manager Registers */ #define FBNIC_QUEUE_TIM_CTL … #define FBNIC_QUEUE_TIM_CTL_MSIX_MASK … #define FBNIC_QUEUE_TIM_THRESHOLD … #define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK … #define FBNIC_QUEUE_TIM_CLEAR … #define FBNIC_QUEUE_TIM_CLEAR_MASK … #define FBNIC_QUEUE_TIM_SET … #define FBNIC_QUEUE_TIM_SET_MASK … #define FBNIC_QUEUE_TIM_MASK … #define FBNIC_QUEUE_TIM_MASK_MASK … #define FBNIC_QUEUE_TIM_TIMER … #define FBNIC_QUEUE_TIM_COUNTS … #define FBNIC_QUEUE_TIM_COUNTS_CNT1_MASK … #define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK … /* Rx Completion Queue Registers */ #define FBNIC_QUEUE_RCQ_CTL … #define FBNIC_QUEUE_RCQ_CTL_RESET … #define FBNIC_QUEUE_RCQ_CTL_ENABLE … #define FBNIC_QUEUE_RCQ_HEAD … #define FBNIC_QUEUE_RCQ_SIZE … #define FBNIC_QUEUE_RCQ_SIZE_MASK … #define FBNIC_QUEUE_RCQ_BAL … #define FBNIC_QUEUE_RCQ_BAH … /* Rx Buffer Descriptor Queue Registers */ #define FBNIC_QUEUE_BDQ_CTL … #define FBNIC_QUEUE_BDQ_CTL_RESET … #define FBNIC_QUEUE_BDQ_CTL_ENABLE … #define FBNIC_QUEUE_BDQ_CTL_PPQ_ENABLE … #define FBNIC_QUEUE_BDQ_HPQ_TAIL … #define FBNIC_QUEUE_BDQ_PPQ_TAIL … #define FBNIC_QUEUE_BDQ_HPQ_SIZE … #define FBNIC_QUEUE_BDQ_PPQ_SIZE … #define FBNIC_QUEUE_BDQ_SIZE_MASK … #define FBNIC_QUEUE_BDQ_HPQ_BAL … #define FBNIC_QUEUE_BDQ_HPQ_BAH … #define FBNIC_QUEUE_BDQ_PPQ_BAL … #define FBNIC_QUEUE_BDQ_PPQ_BAH … /* Rx DMA Engine Configuration */ #define FBNIC_QUEUE_RDE_CTL0 … #define FBNIC_QUEUE_RDE_CTL0_EN_HDR_SPLIT … #define FBNIC_QUEUE_RDE_CTL0_DROP_MODE_MASK … enum { … }; #define FBNIC_QUEUE_RDE_CTL0_MIN_HROOM_MASK … #define FBNIC_QUEUE_RDE_CTL0_MIN_TROOM_MASK … #define FBNIC_QUEUE_RDE_CTL1 … #define FBNIC_QUEUE_RDE_CTL1_MAX_HDR_MASK … #define FBNIC_QUEUE_RDE_CTL1_PAYLD_OFF_MASK … #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PG_CL_MASK … #define FBNIC_QUEUE_RDE_CTL1_PADLEN_MASK … #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK … enum { … }; /* Rx Interrupt Manager Registers */ #define FBNIC_QUEUE_RIM_CTL … #define FBNIC_QUEUE_RIM_CTL_MSIX_MASK … #define FBNIC_QUEUE_RIM_THRESHOLD … #define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK … #define FBNIC_QUEUE_RIM_CLEAR … #define FBNIC_QUEUE_RIM_CLEAR_MASK … #define FBNIC_QUEUE_RIM_SET … #define FBNIC_QUEUE_RIM_SET_MASK … #define FBNIC_QUEUE_RIM_MASK … #define FBNIC_QUEUE_RIM_MASK_MASK … #define FBNIC_QUEUE_RIM_COAL_STATUS … #define FBNIC_QUEUE_RIM_RCD_COUNT_MASK … #define FBNIC_QUEUE_RIM_TIMER_MASK … #define FBNIC_MAX_QUEUES … #define FBNIC_CSR_END_QUEUE … /* BAR 4 CSRs */ /* The IPC mailbox consists of 32 mailboxes, with each mailbox consisting * of 32 4 byte registers. We will use 2 registers per descriptor so the * length of the mailbox is reduced to 16. * * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just * have to do the math and determine the offset based on the mailbox * direction and index inside that mailbox. */ #define FBNIC_IPC_MBX_DESC_LEN … #define FBNIC_IPC_MBX(mbx_idx, desc_idx) … /* Use first register in mailbox to flush writes */ #define FBNIC_FW_ZERO_REG … enum { … }; #define FBNIC_IPC_MBX_DESC_LEN_MASK … #define FBNIC_IPC_MBX_DESC_EOM … #define FBNIC_IPC_MBX_DESC_ADDR_MASK … #define FBNIC_IPC_MBX_DESC_FW_CMPL … #define FBNIC_IPC_MBX_DESC_HOST_CMPL … #endif /* _FBNIC_CSR_H_ */
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