/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Author: Kevin Wells <[email protected]> * * Copyright (C) 2008 NXP Semiconductors * Copyright 2023 Timesys Corporation <[email protected]> */ #ifndef __SOUND_SOC_LPC3XXX_I2S_H #define __SOUND_SOC_LPC3XXX_I2S_H #include <linux/bitfield.h> #include <linux/types.h> #include <linux/regmap.h> struct lpc3xxx_i2s_info { … }; int lpc3xxx_pcm_register(struct platform_device *pdev); /* I2S controller register offsets */ #define LPC3XXX_REG_I2S_DAO … #define LPC3XXX_REG_I2S_DAI … #define LPC3XXX_REG_I2S_TX_FIFO … #define LPC3XXX_REG_I2S_RX_FIFO … #define LPC3XXX_REG_I2S_STAT … #define LPC3XXX_REG_I2S_DMA0 … #define LPC3XXX_REG_I2S_DMA1 … #define LPC3XXX_REG_I2S_IRQ … #define LPC3XXX_REG_I2S_TX_RATE … #define LPC3XXX_REG_I2S_RX_RATE … /* i2s_daO i2s_dai register definitions */ #define LPC3XXX_I2S_WW8 … #define LPC3XXX_I2S_WW16 … #define LPC3XXX_I2S_WW32 … #define LPC3XXX_I2S_MONO … #define LPC3XXX_I2S_STOP … #define LPC3XXX_I2S_RESET … #define LPC3XXX_I2S_WS_SEL … #define LPC3XXX_I2S_WS_HP(s) … #define LPC3XXX_I2S_MUTE … #define LPC3XXX_I2S_WW32_HP … #define LPC3XXX_I2S_WW16_HP … #define LPC3XXX_I2S_WW8_HP … /* i2s_stat register definitions */ #define LPC3XXX_I2S_IRQ_STAT … #define LPC3XXX_I2S_DMA0_REQ … #define LPC3XXX_I2S_DMA1_REQ … /* i2s_dma0 Configuration register definitions */ #define LPC3XXX_I2S_DMA0_RX_EN … #define LPC3XXX_I2S_DMA0_TX_EN … #define LPC3XXX_I2S_DMA0_RX_DEPTH(s) … #define LPC3XXX_I2S_DMA0_TX_DEPTH(s) … /* i2s_dma1 Configuration register definitions */ #define LPC3XXX_I2S_DMA1_RX_EN … #define LPC3XXX_I2S_DMA1_TX_EN … #define LPC3XXX_I2S_DMA1_RX_DEPTH(s) … #define LPC3XXX_I2S_DMA1_TX_DEPTH(s) … /* i2s_irq register definitions */ #define LPC3XXX_I2S_RX_IRQ_EN … #define LPC3XXX_I2S_TX_IRQ_EN … #define LPC3XXX_I2S_IRQ_RX_DEPTH(s) … #define LPC3XXX_I2S_IRQ_TX_DEPTH(s) … #endif
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