linux/drivers/vdpa/octeon_ep/octep_vdpa_hw.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2024 Marvell. */

#include <linux/iopoll.h>

#include "octep_vdpa.h"

enum octep_mbox_ids { … };

#define OCTEP_HW_TIMEOUT …

#define MBOX_OFFSET …
#define MBOX_RSP_MASK …
#define MBOX_RC_MASK …

#define MBOX_RSP_TO_ERR(val) …
#define MBOX_AVAIL(val) …
#define MBOX_RSP(val) …

#define DEV_RST_ACK_BIT …
#define FEATURE_SEL_ACK_BIT …
#define QUEUE_SEL_ACK_BIT …

struct octep_mbox_hdr { … };

struct octep_mbox_sts { … };

struct octep_mbox { … };

static inline struct octep_mbox __iomem *octep_get_mbox(struct octep_hw *oct_hw)
{ … }

static inline int octep_wait_for_mbox_avail(struct octep_mbox __iomem *mbox)
{ … }

static inline int octep_wait_for_mbox_rsp(struct octep_mbox __iomem *mbox)
{ … }

static inline void octep_write_hdr(struct octep_mbox __iomem *mbox, u16 id, u16 sig)
{ … }

static inline u32 octep_read_sig(struct octep_mbox __iomem *mbox)
{ … }

static inline void octep_write_sts(struct octep_mbox __iomem *mbox, u32 sts)
{ … }

static inline u32 octep_read_sts(struct octep_mbox __iomem *mbox)
{ … }

static inline u32 octep_read32_word(struct octep_mbox __iomem *mbox, u16 word_idx)
{ … }

static inline void octep_write32_word(struct octep_mbox __iomem *mbox, u16 word_idx, u32 word)
{ … }

static int octep_process_mbox(struct octep_hw *oct_hw, u16 id, u16 qid, void *buffer,
			      u32 buf_size, bool write)
{ … }

static void octep_mbox_init(struct octep_mbox __iomem *mbox)
{ … }

int octep_verify_features(u64 features)
{ … }

u8 octep_hw_get_status(struct octep_hw *oct_hw)
{ … }

void octep_hw_set_status(struct octep_hw *oct_hw, u8 status)
{ … }

void octep_hw_reset(struct octep_hw *oct_hw)
{ … }

static int feature_sel_write_with_timeout(struct octep_hw *oct_hw, u32 select, void __iomem *addr)
{ … }

u64 octep_hw_get_dev_features(struct octep_hw *oct_hw)
{ … }

u64 octep_hw_get_drv_features(struct octep_hw *oct_hw)
{ … }

void octep_hw_set_drv_features(struct octep_hw *oct_hw, u64 features)
{ … }

void octep_write_queue_select(struct octep_hw *oct_hw, u16 queue_id)
{ … }

void octep_notify_queue(struct octep_hw *oct_hw, u16 qid)
{ … }

void octep_read_dev_config(struct octep_hw *oct_hw, u64 offset, void *dst, int length)
{ … }

int octep_set_vq_address(struct octep_hw *oct_hw, u16 qid, u64 desc_area, u64 driver_area,
			 u64 device_area)
{ … }

int octep_get_vq_state(struct octep_hw *oct_hw, u16 qid, struct vdpa_vq_state *state)
{ … }

int octep_set_vq_state(struct octep_hw *oct_hw, u16 qid, const struct vdpa_vq_state *state)
{ … }

void octep_set_vq_num(struct octep_hw *oct_hw, u16 qid, u32 num)
{ … }

void octep_set_vq_ready(struct octep_hw *oct_hw, u16 qid, bool ready)
{ … }

bool octep_get_vq_ready(struct octep_hw *oct_hw, u16 qid)
{ … }

u16 octep_get_vq_size(struct octep_hw *oct_hw)
{ … }

static u32 octep_get_config_size(struct octep_hw *oct_hw)
{ … }

static void __iomem *octep_get_cap_addr(struct octep_hw *oct_hw, struct virtio_pci_cap *cap)
{ … }

/* In Octeon DPU device, the virtio config space is completely
 * emulated by the device's firmware. So, the standard pci config
 * read apis can't be used for reading the virtio capability.
 */
static void octep_pci_caps_read(struct octep_hw *oct_hw, void *buf, size_t len, off_t offset)
{ … }

static int octep_pci_signature_verify(struct octep_hw *oct_hw)
{ … }

int octep_hw_caps_read(struct octep_hw *oct_hw, struct pci_dev *pdev)
{ … }