/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H #define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H #define NSS_CC_SWITCH_CORE_CLK_SRC … #define NSS_CC_SWITCH_CORE_CLK … #define NSS_CC_APB_BRIDGE_CLK … #define NSS_CC_MAC0_TX_CLK_SRC … #define NSS_CC_MAC0_TX_DIV_CLK_SRC … #define NSS_CC_MAC0_TX_CLK … #define NSS_CC_MAC0_TX_SRDS1_CLK … #define NSS_CC_MAC0_RX_CLK_SRC … #define NSS_CC_MAC0_RX_DIV_CLK_SRC … #define NSS_CC_MAC0_RX_CLK … #define NSS_CC_MAC0_RX_SRDS1_CLK … #define NSS_CC_MAC1_TX_CLK_SRC … #define NSS_CC_MAC1_TX_DIV_CLK_SRC … #define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC … #define NSS_CC_MAC1_SRDS1_CH0_RX_CLK … #define NSS_CC_MAC1_TX_CLK … #define NSS_CC_MAC1_GEPHY0_TX_CLK … #define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK … #define NSS_CC_MAC1_RX_CLK_SRC … #define NSS_CC_MAC1_RX_DIV_CLK_SRC … #define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC … #define NSS_CC_MAC1_SRDS1_CH0_TX_CLK … #define NSS_CC_MAC1_RX_CLK … #define NSS_CC_MAC1_GEPHY0_RX_CLK … #define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK … #define NSS_CC_MAC2_TX_CLK_SRC … #define NSS_CC_MAC2_TX_DIV_CLK_SRC … #define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC … #define NSS_CC_MAC2_SRDS1_CH1_RX_CLK … #define NSS_CC_MAC2_TX_CLK … #define NSS_CC_MAC2_GEPHY1_TX_CLK … #define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK … #define NSS_CC_MAC2_RX_CLK_SRC … #define NSS_CC_MAC2_RX_DIV_CLK_SRC … #define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC … #define NSS_CC_MAC2_SRDS1_CH1_TX_CLK … #define NSS_CC_MAC2_RX_CLK … #define NSS_CC_MAC2_GEPHY1_RX_CLK … #define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK … #define NSS_CC_MAC3_TX_CLK_SRC … #define NSS_CC_MAC3_TX_DIV_CLK_SRC … #define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC … #define NSS_CC_MAC3_SRDS1_CH2_RX_CLK … #define NSS_CC_MAC3_TX_CLK … #define NSS_CC_MAC3_GEPHY2_TX_CLK … #define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK … #define NSS_CC_MAC3_RX_CLK_SRC … #define NSS_CC_MAC3_RX_DIV_CLK_SRC … #define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC … #define NSS_CC_MAC3_SRDS1_CH2_TX_CLK … #define NSS_CC_MAC3_RX_CLK … #define NSS_CC_MAC3_GEPHY2_RX_CLK … #define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK … #define NSS_CC_MAC4_TX_CLK_SRC … #define NSS_CC_MAC4_TX_DIV_CLK_SRC … #define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC … #define NSS_CC_MAC4_SRDS1_CH3_RX_CLK … #define NSS_CC_MAC4_TX_CLK … #define NSS_CC_MAC4_GEPHY3_TX_CLK … #define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK … #define NSS_CC_MAC4_RX_CLK_SRC … #define NSS_CC_MAC4_RX_DIV_CLK_SRC … #define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC … #define NSS_CC_MAC4_SRDS1_CH3_TX_CLK … #define NSS_CC_MAC4_RX_CLK … #define NSS_CC_MAC4_GEPHY3_RX_CLK … #define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK … #define NSS_CC_MAC5_TX_CLK_SRC … #define NSS_CC_MAC5_TX_DIV_CLK_SRC … #define NSS_CC_MAC5_TX_SRDS0_CLK … #define NSS_CC_MAC5_TX_CLK … #define NSS_CC_MAC5_RX_CLK_SRC … #define NSS_CC_MAC5_RX_DIV_CLK_SRC … #define NSS_CC_MAC5_RX_SRDS0_CLK … #define NSS_CC_MAC5_RX_CLK … #define NSS_CC_MAC5_TX_SRDS0_CLK_SRC … #define NSS_CC_MAC5_RX_SRDS0_CLK_SRC … #define NSS_CC_AHB_CLK_SRC … #define NSS_CC_AHB_CLK … #define NSS_CC_SEC_CTRL_AHB_CLK … #define NSS_CC_TLMM_CLK … #define NSS_CC_TLMM_AHB_CLK … #define NSS_CC_CNOC_AHB_CLK … #define NSS_CC_MDIO_AHB_CLK … #define NSS_CC_MDIO_MASTER_AHB_CLK … #define NSS_CC_SYS_CLK_SRC … #define NSS_CC_SRDS0_SYS_CLK … #define NSS_CC_SRDS1_SYS_CLK … #define NSS_CC_GEPHY0_SYS_CLK … #define NSS_CC_GEPHY1_SYS_CLK … #define NSS_CC_GEPHY2_SYS_CLK … #define NSS_CC_GEPHY3_SYS_CLK … #endif
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