linux/drivers/gpu/drm/i915/display/intel_cursor_regs.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2024 Intel Corporation
 */

#ifndef __INTEL_CURSOR_REGS_H__
#define __INTEL_CURSOR_REGS_H__

#include "intel_display_reg_defs.h"

#define _CURACNTR
#define CURCNTR(dev_priv, pipe)
/* Old style CUR*CNTR flags (desktop 8xx) */
#define CURSOR_ENABLE
#define CURSOR_PIPE_GAMMA_ENABLE
#define CURSOR_STRIDE_MASK
#define CURSOR_STRIDE(stride)
#define CURSOR_FORMAT_MASK
#define CURSOR_FORMAT_2C
#define CURSOR_FORMAT_3C
#define CURSOR_FORMAT_4C
#define CURSOR_FORMAT_ARGB
#define CURSOR_FORMAT_XRGB
/* New style CUR*CNTR flags */
#define MCURSOR_ARB_SLOTS_MASK
#define MCURSOR_ARB_SLOTS(x)
#define MCURSOR_PIPE_SEL_MASK
#define MCURSOR_PIPE_SEL(pipe)
#define MCURSOR_PIPE_GAMMA_ENABLE
#define MCURSOR_PIPE_CSC_ENABLE
#define MCURSOR_ROTATE_180
#define MCURSOR_TRICKLE_FEED_DISABLE
#define MCURSOR_MODE_MASK
#define MCURSOR_MODE_DISABLE
#define MCURSOR_MODE_128_32B_AX
#define MCURSOR_MODE_256_32B_AX
#define MCURSOR_MODE_64_2B
#define MCURSOR_MODE_64_32B_AX
#define MCURSOR_MODE_128_ARGB_AX
#define MCURSOR_MODE_256_ARGB_AX
#define MCURSOR_MODE_64_ARGB_AX

#define _CURABASE
#define CURBASE(dev_priv, pipe)

#define _CURAPOS
#define CURPOS(dev_priv, pipe)
#define CURSOR_POS_Y_SIGN
#define CURSOR_POS_Y_MASK
#define CURSOR_POS_Y(y)
#define CURSOR_POS_X_SIGN
#define CURSOR_POS_X_MASK
#define CURSOR_POS_X(x)

#define _CURAPOS_ERLY_TPT
#define CURPOS_ERLY_TPT(dev_priv, pipe)

#define _CURASIZE
#define CURSIZE(dev_priv, pipe)
#define CURSOR_HEIGHT_MASK
#define CURSOR_HEIGHT(h)
#define CURSOR_WIDTH_MASK
#define CURSOR_WIDTH(w)

#define _CUR_FBC_CTL_A
#define CUR_FBC_CTL(dev_priv, pipe)
#define CUR_FBC_EN
#define CUR_FBC_HEIGHT_MASK
#define CUR_FBC_HEIGHT(h)

#define _CUR_CHICKEN_A
#define CUR_CHICKEN(dev_priv, pipe)

#define _CURASURFLIVE
#define CURSURFLIVE(dev_priv, pipe)

/* skl+ */
#define _CUR_WM_A_0
#define _CUR_WM_B_0
#define CUR_WM(pipe, level)
#define CUR_WM_EN
#define CUR_WM_IGNORE_LINES
#define CUR_WM_LINES_MASK
#define CUR_WM_BLOCKS_MASK

#define _CUR_WM_SAGV_A
#define _CUR_WM_SAGV_B
#define CUR_WM_SAGV(pipe)

#define _CUR_WM_SAGV_TRANS_A
#define _CUR_WM_SAGV_TRANS_B
#define CUR_WM_SAGV_TRANS(pipe)

#define _CUR_WM_TRANS_A
#define _CUR_WM_TRANS_B
#define CUR_WM_TRANS(pipe)

#define _CUR_BUF_CFG_A
#define _CUR_BUF_CFG_B
#define CUR_BUF_CFG(pipe)
/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
#define CUR_BUF_END_MASK
#define CUR_BUF_END(end)
#define CUR_BUF_START_MASK
#define CUR_BUF_START(start)

/* tgl+ */
#define _SEL_FETCH_CUR_CTL_A
#define _SEL_FETCH_CUR_CTL_B
#define SEL_FETCH_CUR_CTL(pipe)

#endif /* __INTEL_CURSOR_REGS_H__ */