/* SPDX-License-Identifier: MIT */ /* * Copyright © 2024 Intel Corporation */ #ifndef __INTEL_VRR_REGS_H__ #define __INTEL_VRR_REGS_H__ #include "intel_display_reg_defs.h" /* VRR registers */ #define _TRANS_VRR_CTL_A … #define _TRANS_VRR_CTL_B … #define _TRANS_VRR_CTL_C … #define _TRANS_VRR_CTL_D … #define TRANS_VRR_CTL(dev_priv, trans) … #define VRR_CTL_VRR_ENABLE … #define VRR_CTL_IGN_MAX_SHIFT … #define VRR_CTL_FLIP_LINE_EN … #define VRR_CTL_PIPELINE_FULL_MASK … #define VRR_CTL_PIPELINE_FULL(x) … #define VRR_CTL_PIPELINE_FULL_OVERRIDE … #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK … #define XELPD_VRR_CTL_VRR_GUARDBAND(x) … #define _TRANS_VRR_VMAX_A … #define _TRANS_VRR_VMAX_B … #define _TRANS_VRR_VMAX_C … #define _TRANS_VRR_VMAX_D … #define TRANS_VRR_VMAX(dev_priv, trans) … #define VRR_VMAX_MASK … #define _TRANS_VRR_VMIN_A … #define _TRANS_VRR_VMIN_B … #define _TRANS_VRR_VMIN_C … #define _TRANS_VRR_VMIN_D … #define TRANS_VRR_VMIN(dev_priv, trans) … #define VRR_VMIN_MASK … #define _TRANS_VRR_VMAXSHIFT_A … #define _TRANS_VRR_VMAXSHIFT_B … #define _TRANS_VRR_VMAXSHIFT_C … #define _TRANS_VRR_VMAXSHIFT_D … #define TRANS_VRR_VMAXSHIFT(dev_priv, trans) … #define VRR_VMAXSHIFT_DEC_MASK … #define VRR_VMAXSHIFT_DEC … #define VRR_VMAXSHIFT_INC_MASK … #define _TRANS_VRR_STATUS_A … #define _TRANS_VRR_STATUS_B … #define _TRANS_VRR_STATUS_C … #define _TRANS_VRR_STATUS_D … #define TRANS_VRR_STATUS(dev_priv, trans) … #define VRR_STATUS_VMAX_REACHED … #define VRR_STATUS_NOFLIP_TILL_BNDR … #define VRR_STATUS_FLIP_BEF_BNDR … #define VRR_STATUS_NO_FLIP_FRAME … #define VRR_STATUS_VRR_EN_LIVE … #define VRR_STATUS_FLIPS_SERVICED … #define VRR_STATUS_VBLANK_MASK … #define STATUS_FSM_IDLE … #define STATUS_FSM_WAIT_TILL_FDB … #define STATUS_FSM_WAIT_TILL_FS … #define STATUS_FSM_WAIT_TILL_FLIP … #define STATUS_FSM_PIPELINE_FILL … #define STATUS_FSM_ACTIVE … #define STATUS_FSM_LEGACY_VBLANK … #define _TRANS_VRR_VTOTAL_PREV_A … #define _TRANS_VRR_VTOTAL_PREV_B … #define _TRANS_VRR_VTOTAL_PREV_C … #define _TRANS_VRR_VTOTAL_PREV_D … #define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) … #define VRR_VTOTAL_FLIP_BEFR_BNDR … #define VRR_VTOTAL_FLIP_AFTER_BNDR … #define VRR_VTOTAL_FLIP_AFTER_DBLBUF … #define VRR_VTOTAL_PREV_FRAME_MASK … #define _TRANS_VRR_FLIPLINE_A … #define _TRANS_VRR_FLIPLINE_B … #define _TRANS_VRR_FLIPLINE_C … #define _TRANS_VRR_FLIPLINE_D … #define TRANS_VRR_FLIPLINE(dev_priv, trans) … #define VRR_FLIPLINE_MASK … #define _TRANS_VRR_STATUS2_A … #define _TRANS_VRR_STATUS2_B … #define _TRANS_VRR_STATUS2_C … #define _TRANS_VRR_STATUS2_D … #define TRANS_VRR_STATUS2(dev_priv, trans) … #define VRR_STATUS2_VERT_LN_CNT_MASK … #define _TRANS_PUSH_A … #define _TRANS_PUSH_B … #define _TRANS_PUSH_C … #define _TRANS_PUSH_D … #define TRANS_PUSH(dev_priv, trans) … #define TRANS_PUSH_EN … #define TRANS_PUSH_SEND … #define _TRANS_VRR_VSYNC_A … #define TRANS_VRR_VSYNC(dev_priv, trans) … #define VRR_VSYNC_END_MASK … #define VRR_VSYNC_END(vsync_end) … #define VRR_VSYNC_START_MASK … #define VRR_VSYNC_START(vsync_start) … /*CMRR Registers*/ #define _TRANS_CMRR_M_LO_A … #define TRANS_CMRR_M_LO(dev_priv, trans) … #define _TRANS_CMRR_M_HI_A … #define TRANS_CMRR_M_HI(dev_priv, trans) … #define _TRANS_CMRR_N_LO_A … #define TRANS_CMRR_N_LO(dev_priv, trans) … #define _TRANS_CMRR_N_HI_A … #define TRANS_CMRR_N_HI(dev_priv, trans) … #define VRR_CTL_CMRR_ENABLE … #endif /* __INTEL_VRR_REGS__ */
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