linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

/* SPDX-License-Identifier: MIT */
/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "reg_helper.h"
#include "core_types.h"
#include "resource.h"
#include "dcn35_dccg.h"

#define TO_DCN_DCCG(dccg) …

#define REG(reg) …

#undef FN
#define FN(reg_name, field_name) …

#define CTX …
#define DC_LOGGER …

enum symclk_fe_source { … };

enum symclk_be_source { … };

enum physymclk_source { … };

enum dtbclk_source { … };

enum dppclk_clock_source { … };

enum dp_stream_clk_source { … };

enum hdmi_char_clk { … };

enum hdmi_stream_clk_source { … };

enum symclk32_se_clk_source { … };

enum symclk32_le_clk_source { … };

enum dsc_clk_source { … };


static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool enable)
{ … }

static void dccg35_set_symclk32_se_rcg(
	struct dccg *dccg,
	int inst,
	bool enable)
{ … }

static void dccg35_set_symclk32_le_rcg(
	struct dccg *dccg,
	int inst,
	bool enable)
{ … }

static void dccg35_set_physymclk_rcg(
	struct dccg *dccg,
	int inst,
	bool enable)
{ … }

static void dccg35_set_symclk_fe_rcg(
	struct dccg *dccg,
	int inst,
	bool enable)
{ … }

static void dccg35_set_symclk_be_rcg(
	struct dccg *dccg,
	int inst,
	bool enable)
{ … }

static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)
{ … }

static void dccg35_set_dppclk_rcg(struct dccg *dccg,
												int inst, bool enable)
{ … }

static void dccg35_set_dpstreamclk_rcg(
	struct dccg *dccg,
	int inst,
	bool enable)
{ … }

static void dccg35_set_smclk32_se_rcg(
		struct dccg *dccg,
		int inst,
		bool enable)
{ … }

static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)
{ … }

static void dccg35_set_symclk32_se_src_new(
	struct dccg *dccg,
	int inst,
	enum symclk32_se_clk_source src
	)
{ … }

static int
dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)
{ … }


static void dccg35_set_symclk32_le_src_new(
	struct dccg *dccg,
	int inst,
	enum symclk32_le_clk_source src)
{ … }

static void dcn35_set_dppclk_src_new(struct dccg *dccg,
				 int inst, enum dppclk_clock_source src)
{ … }

static void dccg35_set_dtbclk_p_src_new(
	struct dccg *dccg,
	enum dtbclk_source src,
	int inst)
{ … }

static void dccg35_set_dpstreamclk_src_new(
	struct dccg *dccg,
	enum dp_stream_clk_source src,
	int inst)
{ … }

static void dccg35_set_physymclk_src_new(
	struct dccg *dccg,
	enum physymclk_source src,
	int inst)
{ … }

static void dccg35_set_symclk_be_src_new(
	struct dccg *dccg,
	enum symclk_be_source src,
	int inst)
{ … }

static int dccg35_is_symclk_fe_src_functional_be(struct dccg *dccg,
												 int symclk_fe_inst,
												 int symclk_be_inst)
{ … }

static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)
{ … }

static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)
{ … }

static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)
{ … }

static void dccg35_enable_symclk_fe_new(
	struct dccg *dccg,
	int inst,
	enum symclk_fe_source src)
{ … }

static void dccg35_disable_symclk_fe_new(
	struct dccg *dccg,
	int inst)
{ … }

static void dccg35_enable_symclk_be_new(
	struct dccg *dccg,
	int inst,
	enum symclk_be_source src)
{ … }

static void dccg35_disable_symclk_be_new(
	struct dccg *dccg,
	int inst)
{ … }

static void dccg35_enable_symclk32_se_new(
	struct dccg *dccg,
	int inst,
	enum symclk32_se_clk_source src)
{ … }

static void dccg35_disable_symclk32_se_new(
	struct dccg *dccg,
	int inst)
{ … }

static void dccg35_enable_symclk32_le_new(
	struct dccg *dccg,
	int inst,
	enum symclk32_le_clk_source src)
{ … }

static void dccg35_disable_symclk32_le_new(
	struct dccg *dccg,
	int inst)
{ … }

static void dccg35_enable_physymclk_new(struct dccg *dccg,
					int inst,
					enum physymclk_source src)
{ … }

static void dccg35_disable_physymclk_new(struct dccg *dccg,
										 int inst)
{ … }

static void dccg35_enable_dpp_clk_new(
	struct dccg *dccg,
	int inst,
	enum dppclk_clock_source src)
{ … }

static void dccg35_disable_dpp_clk_new(
	struct dccg *dccg,
	int inst)
{ … }

static void dccg35_disable_dscclk_new(struct dccg *dccg,
									  int inst)
{ … }

static void dccg35_enable_dscclk_new(struct dccg *dccg,
									 int inst,
									 enum dsc_clk_source src)
{ … }

static void dccg35_enable_dtbclk_p_new(struct dccg *dccg,
									   enum dtbclk_source src,
									   int inst)
{ … }

static void dccg35_disable_dtbclk_p_new(struct dccg *dccg,
										int inst)
{ … }

static void dccg35_disable_dpstreamclk_new(struct dccg *dccg,
										  int inst)
{ … }

static void dccg35_enable_dpstreamclk_new(struct dccg *dccg,
										   enum dp_stream_clk_source src,
										   int inst)
{ … }

static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)
{ … }

static void dcn35_set_dppclk_enable(struct dccg *dccg,
				 uint32_t dpp_inst, uint32_t enable)
{ … }

static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,
				  int req_dppclk)
{ … }

static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,
		 uint32_t dpp_inst, uint32_t enable)
{ … }

static void dccg35_get_pixel_rate_div(
		struct dccg *dccg,
		uint32_t otg_inst,
		uint32_t *k1,
		uint32_t *k2)
{ … }

static void dccg35_set_pixel_rate_div(
		struct dccg *dccg,
		uint32_t otg_inst,
		enum pixel_rate_div k1,
		enum pixel_rate_div k2)
{ … }

static void dccg35_set_dtbclk_p_src(
		struct dccg *dccg,
		enum streamclk_source src,
		uint32_t otg_inst)
{ … }

/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
static void dccg35_set_dtbclk_dto(
		struct dccg *dccg,
		const struct dtbclk_dto_params *params)
{ … }

static void dccg35_set_dpstreamclk(
		struct dccg *dccg,
		enum streamclk_source src,
		int otg_inst,
		int dp_hpo_inst)
{ … }


static void dccg35_set_dpstreamclk_root_clock_gating(
		struct dccg *dccg,
		int dp_hpo_inst,
		bool enable)
{ … }



static void dccg35_set_physymclk_root_clock_gating(
		struct dccg *dccg,
		int phy_inst,
		bool enable)
{ … }

static void dccg35_set_physymclk(
		struct dccg *dccg,
		int phy_inst,
		enum physymclk_clock_source clk_src,
		bool force_enable)
{ … }

static void dccg35_set_valid_pixel_rate(
		struct dccg *dccg,
		int ref_dtbclk_khz,
		int otg_inst,
		int pixclk_khz)
{ … }

static void dccg35_dpp_root_clock_control(
		struct dccg *dccg,
		unsigned int dpp_inst,
		bool clock_on)
{ … }

static void dccg35_disable_symclk32_se(
		struct dccg *dccg,
		int hpo_se_inst)
{ … }

static void dccg35_init_cb(struct dccg *dccg)
{ … }

void dccg35_init(struct dccg *dccg)
{ … }

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)
{ … }

static void dccg35_enable_dscclk(struct dccg *dccg, int inst)
{ … }

static void dccg35_disable_dscclk(struct dccg *dccg,
				int inst)
{ … }

static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
{ … }

/*get other front end connected to this backend*/
static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)
{ … }

static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
{ … }

static void dccg35_set_dpstreamclk_cb(
		struct dccg *dccg,
		enum streamclk_source src,
		int otg_inst,
		int dp_hpo_inst)
{ … }

static void dccg35_set_dpstreamclk_root_clock_gating_cb(
	struct dccg *dccg,
	int dp_hpo_inst,
	bool power_on)
{ … }

static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,
				  int req_dppclk)
{ … }

static void dccg35_dpp_root_clock_control_cb(
	struct dccg *dccg,
	unsigned int dpp_inst,
	bool power_on)
{ … }

static void dccg35_enable_symclk32_se_cb(
	struct dccg *dccg,
	int inst,
	enum phyd32clk_clock_source phyd32clk)
{ … }

static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)
{ … }

static void dccg35_enable_symclk32_le_cb(
			struct dccg *dccg,
			int inst,
			enum phyd32clk_clock_source src)
{ … }

static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)
{ … }

static void dccg35_set_symclk32_le_root_clock_gating_cb(
	struct dccg *dccg,
	int inst,
	bool power_on)
{ … }

static void dccg35_set_physymclk_cb(
	struct dccg *dccg,
	int inst,
	enum physymclk_clock_source clk_src,
	bool force_enable)
{ … }

static void dccg35_set_physymclk_root_clock_gating_cb(
	struct dccg *dccg,
	int inst,
	bool power_on)
{ … }

static void dccg35_set_symclk32_le_root_clock_gating(
	struct dccg *dccg,
	int inst,
	bool power_on)
{ … }

static void dccg35_set_dtbclk_p_src_cb(
		struct dccg *dccg,
		enum streamclk_source src,
		uint32_t inst)
{ … }

static void dccg35_set_dtbclk_dto_cb(
		struct dccg *dccg,
		const struct dtbclk_dto_params *params)
{ … }

static void dccg35_disable_dscclk_cb(struct dccg *dccg,
									 int inst)
{ … }

static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)
{ … }

static void dccg35_enable_symclk_se_cb(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)
{ … }

static void dccg35_disable_symclk_se_cb(
			struct dccg *dccg,
			uint32_t stream_enc_inst,
			uint32_t link_enc_inst)
{ … }

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)
{ … }

static const struct dccg_funcs dccg35_funcs_new = …;

static const struct dccg_funcs dccg35_funcs = …;

struct dccg *dccg35_create(
	struct dc_context *ctx,
	const struct dccg_registers *regs,
	const struct dccg_shift *dccg_shift,
	const struct dccg_mask *dccg_mask)
{ … }