linux/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2020-2023 Intel Corporation
 */

#ifndef __IVPU_HW_BTRS_MTL_REG_H__
#define __IVPU_HW_BTRS_MTL_REG_H__

#include <linux/bits.h>

#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE …

#define VPU_HW_BTRS_MTL_INTERRUPT_STAT …
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK …
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK …
#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK …

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 …
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK …
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK …

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 …
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK …
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK …

#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 …
#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK …

#define VPU_HW_BTRS_MTL_WP_REQ_CMD …
#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK …

#define VPU_HW_BTRS_MTL_WP_DOWNLOAD …
#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK …

#define VPU_HW_BTRS_MTL_CURRENT_PLL …
#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK …

#define VPU_HW_BTRS_MTL_PLL_ENABLE …

#define VPU_HW_BTRS_MTL_FMIN_FUSE …
#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK …
#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK …

#define VPU_HW_BTRS_MTL_FMAX_FUSE …
#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK …

#define VPU_HW_BTRS_MTL_TILE_FUSE …
#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK …
#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK …

#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK …
#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK …

#define VPU_HW_BTRS_MTL_PLL_STATUS …
#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK …

#define VPU_HW_BTRS_MTL_VPU_STATUS …
#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK …
#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK …

#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL …
#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK …
#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK …

#define VPU_HW_BTRS_MTL_VPU_IP_RESET …
#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK …

#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET …
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE …
#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE …

#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 …
#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 …
#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR …

#define VPU_HW_BTRS_MTL_UFI_ERR_LOG …
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK …
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK …
#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK …

#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR …

#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */