// SPDX-License-Identifier: GPL-2.0-only /* * STM32 DMA3 controller driver * * Copyright (C) STMicroelectronics 2024 * Author(s): Amelie Delaunay <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> #include <linux/dmapool.h> #include <linux/init.h> #include <linux/iopoll.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of_dma.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> #include "../virt-dma.h" #define STM32_DMA3_SECCFGR … #define STM32_DMA3_PRIVCFGR … #define STM32_DMA3_RCFGLOCKR … #define STM32_DMA3_MISR … #define STM32_DMA3_SMISR … #define STM32_DMA3_CLBAR(x) … #define STM32_DMA3_CCIDCFGR(x) … #define STM32_DMA3_CSEMCR(x) … #define STM32_DMA3_CFCR(x) … #define STM32_DMA3_CSR(x) … #define STM32_DMA3_CCR(x) … #define STM32_DMA3_CTR1(x) … #define STM32_DMA3_CTR2(x) … #define STM32_DMA3_CBR1(x) … #define STM32_DMA3_CSAR(x) … #define STM32_DMA3_CDAR(x) … #define STM32_DMA3_CLLR(x) … #define STM32_DMA3_HWCFGR13 … #define STM32_DMA3_HWCFGR12 … #define STM32_DMA3_HWCFGR4 … #define STM32_DMA3_HWCFGR3 … #define STM32_DMA3_HWCFGR2 … #define STM32_DMA3_HWCFGR1 … #define STM32_DMA3_VERR … /* SECCFGR DMA secure configuration register */ #define SECCFGR_SEC(x) … /* MISR DMA non-secure/secure masked interrupt status register */ #define MISR_MIS(x) … /* CxLBAR DMA channel x linked_list base address register */ #define CLBAR_LBA … /* CxCIDCFGR DMA channel x CID register */ #define CCIDCFGR_CFEN … #define CCIDCFGR_SEM_EN … #define CCIDCFGR_SCID … #define CCIDCFGR_SEM_WLIST_CID0 … #define CCIDCFGR_SEM_WLIST_CID1 … #define CCIDCFGR_SEM_WLIST_CID2 … enum ccidcfgr_cid { … }; /* CxSEMCR DMA channel x semaphore control register */ #define CSEMCR_SEM_MUTEX … #define CSEMCR_SEM_CCID … /* CxFCR DMA channel x flag clear register */ #define CFCR_TCF … #define CFCR_HTF … #define CFCR_DTEF … #define CFCR_ULEF … #define CFCR_USEF … #define CFCR_SUSPF … /* CxSR DMA channel x status register */ #define CSR_IDLEF … #define CSR_TCF … #define CSR_HTF … #define CSR_DTEF … #define CSR_ULEF … #define CSR_USEF … #define CSR_SUSPF … #define CSR_ALL_F … #define CSR_FIFOL … /* CxCR DMA channel x control register */ #define CCR_EN … #define CCR_RESET … #define CCR_SUSP … #define CCR_TCIE … #define CCR_HTIE … #define CCR_DTEIE … #define CCR_ULEIE … #define CCR_USEIE … #define CCR_SUSPIE … #define CCR_ALLIE … #define CCR_LSM … #define CCR_LAP … #define CCR_PRIO … enum ccr_prio { … }; /* CxTR1 DMA channel x transfer register 1 */ #define CTR1_SINC … #define CTR1_SBL_1 … #define CTR1_DINC … #define CTR1_DBL_1 … #define CTR1_SDW_LOG2 … #define CTR1_PAM … #define CTR1_SAP … #define CTR1_DDW_LOG2 … #define CTR1_DAP … enum ctr1_dw { … }; enum ctr1_pam { … }; /* CxTR2 DMA channel x transfer register 2 */ #define CTR2_REQSEL … #define CTR2_SWREQ … #define CTR2_DREQ … #define CTR2_BREQ … #define CTR2_PFREQ … #define CTR2_TCEM … enum ctr2_tcem { … }; /* CxBR1 DMA channel x block register 1 */ #define CBR1_BNDT … /* CxLLR DMA channel x linked-list address register */ #define CLLR_LA … #define CLLR_ULL … #define CLLR_UDA … #define CLLR_USA … #define CLLR_UB1 … #define CLLR_UT2 … #define CLLR_UT1 … /* HWCFGR13 DMA hardware configuration register 13 x=8..15 */ /* HWCFGR12 DMA hardware configuration register 12 x=0..7 */ #define G_PER_CTRL(x) … /* HWCFGR4 DMA hardware configuration register 4 x=8..15 */ /* HWCFGR3 DMA hardware configuration register 3 x=0..7 */ #define G_FIFO_SIZE(x) … #define get_chan_hwcfg(x, mask, reg) … /* HWCFGR2 DMA hardware configuration register 2 */ #define G_MAX_REQ_ID … /* HWCFGR1 DMA hardware configuration register 1 */ #define G_MASTER_PORTS … #define G_NUM_CHANNELS … #define G_M0_DATA_WIDTH_ENC … #define G_M1_DATA_WIDTH_ENC … enum stm32_dma3_master_ports { … }; enum stm32_dma3_port_data_width { … }; /* VERR DMA version register */ #define VERR_MINREV … #define VERR_MAJREV … /* Device tree */ /* struct stm32_dma3_dt_conf */ /* .ch_conf */ #define STM32_DMA3_DT_PRIO … #define STM32_DMA3_DT_FIFO … /* .tr_conf */ #define STM32_DMA3_DT_SINC … #define STM32_DMA3_DT_SAP … #define STM32_DMA3_DT_DINC … #define STM32_DMA3_DT_DAP … #define STM32_DMA3_DT_BREQ … #define STM32_DMA3_DT_PFREQ … #define STM32_DMA3_DT_TCEM … /* struct stm32_dma3_chan .config_set bitfield */ #define STM32_DMA3_CFG_SET_DT … #define STM32_DMA3_CFG_SET_DMA … #define STM32_DMA3_CFG_SET_BOTH … #define STM32_DMA3_MAX_BLOCK_SIZE … #define port_is_ahb(maxdw) … #define port_is_axi(maxdw) … #define get_chan_max_dw(maxdw, maxburst) … /* Static linked-list data structure (depends on update bits UT1/UT2/UB1/USA/UDA/ULL) */ struct stm32_dma3_hwdesc { … } __packed __aligned(…); /* * CLLR_LA / sizeof(struct stm32_dma3_hwdesc) represents the number of hdwdesc that can be addressed * by the pointer to the next linked-list data structure. The __aligned forces the 32-byte * alignment. So use hardcoded 32. Multiplied by the max block size of each item, it represents * the sg size limitation. */ #define STM32_DMA3_MAX_SEG_SIZE … /* * Linked-list items */ struct stm32_dma3_lli { … }; struct stm32_dma3_swdesc { … }; struct stm32_dma3_dt_conf { … }; struct stm32_dma3_chan { … }; struct stm32_dma3_ddata { … }; static inline struct stm32_dma3_ddata *to_stm32_dma3_ddata(struct stm32_dma3_chan *chan) { … } static inline struct stm32_dma3_chan *to_stm32_dma3_chan(struct dma_chan *c) { … } static inline struct stm32_dma3_swdesc *to_stm32_dma3_swdesc(struct virt_dma_desc *vdesc) { … } static struct device *chan2dev(struct stm32_dma3_chan *chan) { … } static void stm32_dma3_chan_dump_reg(struct stm32_dma3_chan *chan) { … } static void stm32_dma3_chan_dump_hwdesc(struct stm32_dma3_chan *chan, struct stm32_dma3_swdesc *swdesc) { … } static struct stm32_dma3_swdesc *stm32_dma3_chan_desc_alloc(struct stm32_dma3_chan *chan, u32 count) { … } static void stm32_dma3_chan_desc_free(struct stm32_dma3_chan *chan, struct stm32_dma3_swdesc *swdesc) { … } static void stm32_dma3_chan_vdesc_free(struct virt_dma_desc *vdesc) { … } static void stm32_dma3_check_user_setting(struct stm32_dma3_chan *chan) { … } static void stm32_dma3_chan_prep_hwdesc(struct stm32_dma3_chan *chan, struct stm32_dma3_swdesc *swdesc, u32 curr, dma_addr_t src, dma_addr_t dst, u32 len, u32 ctr1, u32 ctr2, bool is_last, bool is_cyclic) { … } static enum dma_slave_buswidth stm32_dma3_get_max_dw(u32 chan_max_burst, enum stm32_dma3_port_data_width port_max_dw, u32 len, dma_addr_t addr) { … } static u32 stm32_dma3_get_max_burst(u32 len, enum dma_slave_buswidth dw, u32 chan_max_burst) { … } static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transfer_direction dir, u32 *ccr, u32 *ctr1, u32 *ctr2, dma_addr_t src_addr, dma_addr_t dst_addr, u32 len) { … } static void stm32_dma3_chan_start(struct stm32_dma3_chan *chan) { … } static int stm32_dma3_chan_suspend(struct stm32_dma3_chan *chan, bool susp) { … } static void stm32_dma3_chan_reset(struct stm32_dma3_chan *chan) { … } static int stm32_dma3_chan_get_curr_hwdesc(struct stm32_dma3_swdesc *swdesc, u32 cllr, u32 *residue) { … } static void stm32_dma3_chan_set_residue(struct stm32_dma3_chan *chan, struct stm32_dma3_swdesc *swdesc, struct dma_tx_state *txstate) { … } static int stm32_dma3_chan_stop(struct stm32_dma3_chan *chan) { … } static void stm32_dma3_chan_complete(struct stm32_dma3_chan *chan) { … } static irqreturn_t stm32_dma3_chan_irq(int irq, void *devid) { … } static int stm32_dma3_alloc_chan_resources(struct dma_chan *c) { … } static void stm32_dma3_free_chan_resources(struct dma_chan *c) { … } static void stm32_dma3_init_chan_config_for_memcpy(struct stm32_dma3_chan *chan, dma_addr_t dst, dma_addr_t src) { … } static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dst, dma_addr_t src, size_t len, unsigned long flags) { … } static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan *c, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction dir, unsigned long flags, void *context) { … } static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_cyclic(struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction dir, unsigned long flags) { … } static void stm32_dma3_caps(struct dma_chan *c, struct dma_slave_caps *caps) { … } static int stm32_dma3_config(struct dma_chan *c, struct dma_slave_config *config) { … } static int stm32_dma3_pause(struct dma_chan *c) { … } static int stm32_dma3_resume(struct dma_chan *c) { … } static int stm32_dma3_terminate_all(struct dma_chan *c) { … } static void stm32_dma3_synchronize(struct dma_chan *c) { … } static enum dma_status stm32_dma3_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *txstate) { … } static void stm32_dma3_issue_pending(struct dma_chan *c) { … } static bool stm32_dma3_filter_fn(struct dma_chan *c, void *fn_param) { … } static struct dma_chan *stm32_dma3_of_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { … } static u32 stm32_dma3_check_rif(struct stm32_dma3_ddata *ddata) { … } static const struct of_device_id stm32_dma3_of_match[] = …; MODULE_DEVICE_TABLE(of, stm32_dma3_of_match); static int stm32_dma3_probe(struct platform_device *pdev) { … } static void stm32_dma3_remove(struct platform_device *pdev) { … } static int stm32_dma3_runtime_suspend(struct device *dev) { … } static int stm32_dma3_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops stm32_dma3_pm_ops = …; static struct platform_driver stm32_dma3_driver = …; static int __init stm32_dma3_init(void) { … } subsys_initcall(stm32_dma3_init); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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