#ifndef KFD_SYSFS_H_INCLUDED
#define KFD_SYSFS_H_INCLUDED
#define HSA_CAP_HOT_PLUGGABLE …
#define HSA_CAP_ATS_PRESENT …
#define HSA_CAP_SHARED_WITH_GRAPHICS …
#define HSA_CAP_QUEUE_SIZE_POW2 …
#define HSA_CAP_QUEUE_SIZE_32BIT …
#define HSA_CAP_QUEUE_IDLE_EVENT …
#define HSA_CAP_VA_LIMIT …
#define HSA_CAP_WATCH_POINTS_SUPPORTED …
#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK …
#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT …
#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK …
#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT …
#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 …
#define HSA_CAP_DOORBELL_TYPE_1_0 …
#define HSA_CAP_DOORBELL_TYPE_2_0 …
#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP …
#define HSA_CAP_TRAP_DEBUG_SUPPORT …
#define HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED …
#define HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED …
#define HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED …
#define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED …
#define HSA_CAP_MEM_EDCSUPPORTED …
#define HSA_CAP_RASEVENTNOTIFY …
#define HSA_CAP_ASIC_REVISION_MASK …
#define HSA_CAP_ASIC_REVISION_SHIFT …
#define HSA_CAP_SRAM_EDCSUPPORTED …
#define HSA_CAP_SVMAPI_SUPPORTED …
#define HSA_CAP_FLAGS_COHERENTHOSTACCESS …
#define HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED …
#define HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED …
#define HSA_CAP_RESERVED …
#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK …
#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_SHIFT …
#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_MASK …
#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT …
#define HSA_DBG_DISPATCH_INFO_ALWAYS_VALID …
#define HSA_DBG_WATCHPOINTS_EXCLUSIVE …
#define HSA_DBG_RESERVED …
#define HSA_MEM_HEAP_TYPE_SYSTEM …
#define HSA_MEM_HEAP_TYPE_FB_PUBLIC …
#define HSA_MEM_HEAP_TYPE_FB_PRIVATE …
#define HSA_MEM_HEAP_TYPE_GPU_GDS …
#define HSA_MEM_HEAP_TYPE_GPU_LDS …
#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH …
#define HSA_MEM_FLAGS_HOT_PLUGGABLE …
#define HSA_MEM_FLAGS_NON_VOLATILE …
#define HSA_MEM_FLAGS_RESERVED …
#define HSA_CACHE_TYPE_DATA …
#define HSA_CACHE_TYPE_INSTRUCTION …
#define HSA_CACHE_TYPE_CPU …
#define HSA_CACHE_TYPE_HSACU …
#define HSA_CACHE_TYPE_RESERVED …
#define HSA_IOLINK_TYPE_UNDEFINED …
#define HSA_IOLINK_TYPE_HYPERTRANSPORT …
#define HSA_IOLINK_TYPE_PCIEXPRESS …
#define HSA_IOLINK_TYPE_AMBA …
#define HSA_IOLINK_TYPE_MIPI …
#define HSA_IOLINK_TYPE_QPI_1_1 …
#define HSA_IOLINK_TYPE_RESERVED1 …
#define HSA_IOLINK_TYPE_RESERVED2 …
#define HSA_IOLINK_TYPE_RAPID_IO …
#define HSA_IOLINK_TYPE_INFINIBAND …
#define HSA_IOLINK_TYPE_RESERVED3 …
#define HSA_IOLINK_TYPE_XGMI …
#define HSA_IOLINK_TYPE_XGOP …
#define HSA_IOLINK_TYPE_GZ …
#define HSA_IOLINK_TYPE_ETHERNET_RDMA …
#define HSA_IOLINK_TYPE_RDMA_OTHER …
#define HSA_IOLINK_TYPE_OTHER …
#define HSA_IOLINK_FLAGS_ENABLED …
#define HSA_IOLINK_FLAGS_NON_COHERENT …
#define HSA_IOLINK_FLAGS_NO_ATOMICS_32_BIT …
#define HSA_IOLINK_FLAGS_NO_ATOMICS_64_BIT …
#define HSA_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA …
#define HSA_IOLINK_FLAGS_RESERVED …
#endif