linux/drivers/clk/sophgo/clk-cv18xx-ip.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2023 Inochi Amaoto <[email protected]>
 */

#ifndef _CLK_SOPHGO_CV1800_IP_H_
#define _CLK_SOPHGO_CV1800_IP_H_

#include "clk-cv18xx-common.h"

struct cv1800_clk_gate {};

struct cv1800_clk_div_data {};

struct cv1800_clk_div {};

struct cv1800_clk_bypass_div {};

struct cv1800_clk_mux {};

struct cv1800_clk_bypass_mux {};

struct cv1800_clk_mmux {};

struct cv1800_clk_audio {};

#define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags)

#define _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift,		\
		    _div_reg, _div_shift, _div_width, _div_init,	\
		    _div_flag, _ops, _flags)

#define _CV1800_FIXED_DIV_FLAG

#define _CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift,	\
			  _fix_div, _ops, _flags)

#define CV1800_DIV(_name, _parent, _gate_reg, _gate_shift,		\
		   _div_reg, _div_shift, _div_width, _div_init,		\
		   _div_flag, _flags)

#define CV1800_BYPASS_DIV(_name, _parent, _gate_reg, _gate_shift,	\
			  _div_reg, _div_shift, _div_width, _div_init,	\
			  _div_flag, _bypass_reg, _bypass_shift, _flags)

#define CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift,	\
			 _fix_div, _flags)		\

#define CV1800_BYPASS_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift,	\
				_fix_div, _bypass_reg, _bypass_shift,	\
				_flags)

#define _CV1800_MUX(_name, _parent, _gate_reg, _gate_shift,		\
		    _div_reg, _div_shift, _div_width, _div_init,	\
		    _div_flag,						\
		    _mux_reg, _mux_shift, _mux_width,			\
		    _ops, _flags)

#define CV1800_MUX(_name, _parent, _gate_reg, _gate_shift,		\
		   _div_reg, _div_shift, _div_width, _div_init,		\
		   _div_flag,						\
		   _mux_reg, _mux_shift, _mux_width, _flags)

#define CV1800_BYPASS_MUX(_name, _parent, _gate_reg, _gate_shift,	\
			  _div_reg, _div_shift, _div_width, _div_init,	\
			  _div_flag,					\
			  _mux_reg, _mux_shift, _mux_width,		\
			  _bypass_reg, _bypass_shift, _flags)

#define CV1800_MMUX(_name, _parent, _gate_reg, _gate_shift,		\
		    _div0_reg, _div0_shift, _div0_width, _div0_init,	\
		    _div0_flag,						\
		    _div1_reg, _div1_shift, _div1_width, _div1_init,	\
		    _div1_flag,						\
		    _mux0_reg, _mux0_shift, _mux0_width,		\
		    _mux1_reg, _mux1_shift, _mux1_width,		\
		    _bypass_reg, _bypass_shift,				\
		    _clk_sel_reg, _clk_sel_shift,			\
		    _parent2sel, _sel2parent0, _sel2parent1, _flags)

#define CV1800_ACLK(_name, _parent,					\
		    _src_en_reg, _src_en_reg_shift,			\
		    _output_en_reg, _output_en_shift,			\
		    _div_en_reg, _div_en_reg_shift,			\
		    _div_up_reg, _div_up_reg_shift,			\
		    _m_reg, _m_shift, _m_width, _m_flag,		\
		    _n_reg, _n_shift, _n_width, _n_flag,		\
		    _target_rate, _flags)

extern const struct clk_ops cv1800_clk_gate_ops;
extern const struct clk_ops cv1800_clk_div_ops;
extern const struct clk_ops cv1800_clk_bypass_div_ops;
extern const struct clk_ops cv1800_clk_mux_ops;
extern const struct clk_ops cv1800_clk_bypass_mux_ops;
extern const struct clk_ops cv1800_clk_mmux_ops;
extern const struct clk_ops cv1800_clk_audio_ops;

#endif // _CLK_SOPHGO_CV1800_IP_H_