/* SPDX-License-Identifier: MIT */ /* Copyright © 2024 Intel Corporation */ #ifndef __INTEL_FBC_REGS__ #define __INTEL_FBC_REGS__ #include "intel_display_reg_defs.h" #define FBC_CFB_BASE … #define FBC_LL_BASE … #define FBC_CONTROL … #define FBC_CTL_EN … #define FBC_CTL_PERIODIC … #define FBC_CTL_INTERVAL_MASK … #define FBC_CTL_INTERVAL(x) … #define FBC_CTL_STOP_ON_MOD … #define FBC_CTL_UNCOMPRESSIBLE … #define FBC_CTL_C3_IDLE … #define FBC_CTL_STRIDE_MASK … #define FBC_CTL_STRIDE(x) … #define FBC_CTL_FENCENO_MASK … #define FBC_CTL_FENCENO(x) … #define FBC_COMMAND … #define FBC_CMD_COMPRESS … #define FBC_STATUS … #define FBC_STAT_COMPRESSING … #define FBC_STAT_COMPRESSED … #define FBC_STAT_MODIFIED … #define FBC_STAT_CURRENT_LINE_MASK … #define FBC_CONTROL2 … #define FBC_CTL_FENCE_DBL … #define FBC_CTL_IDLE_MASK … #define FBC_CTL_IDLE_IMM … #define FBC_CTL_IDLE_FULL … #define FBC_CTL_IDLE_LINE … #define FBC_CTL_IDLE_DEBUG … #define FBC_CTL_CPU_FENCE_EN … #define FBC_CTL_PLANE_MASK … #define FBC_CTL_PLANE(i9xx_plane) … #define FBC_FENCE_OFF … #define FBC_MOD_NUM … #define FBC_MOD_NUM_MASK … #define FBC_MOD_NUM_VALID … #define FBC_TAG(i) … #define FBC_TAG_MASK … #define FBC_TAG_MODIFIED … #define FBC_TAG_UNCOMPRESSED … #define FBC_TAG_UNCOMPRESSIBLE … #define FBC_TAG_COMPRESSED … #define FBC_LL_SIZE … #define DPFC_CB_BASE … #define ILK_DPFC_CB_BASE(fbc_id) … #define DPFC_CONTROL … #define ILK_DPFC_CONTROL(fbc_id) … #define DPFC_CTL_EN … #define DPFC_CTL_PLANE_MASK_G4X … #define DPFC_CTL_PLANE_G4X(i9xx_plane) … #define DPFC_CTL_FENCE_EN_G4X … #define DPFC_CTL_PLANE_MASK_IVB … #define DPFC_CTL_PLANE_IVB(i9xx_plane) … #define DPFC_CTL_FENCE_EN_IVB … #define DPFC_CTL_PERSISTENT_MODE … #define DPFC_CTL_PLANE_BINDING_MASK … #define DPFC_CTL_PLANE_BINDING(plane_id) … #define DPFC_CTL_FALSE_COLOR … #define DPFC_CTL_SR_EN … #define DPFC_CTL_SR_EXIT_DIS … #define DPFC_CTL_LIMIT_MASK … #define DPFC_CTL_LIMIT_1X … #define DPFC_CTL_LIMIT_2X … #define DPFC_CTL_LIMIT_4X … #define DPFC_CTL_FENCENO_MASK … #define DPFC_CTL_FENCENO(fence) … #define DPFC_RECOMP_CTL … #define ILK_DPFC_RECOMP_CTL(fbc_id) … #define DPFC_RECOMP_STALL_EN … #define DPFC_RECOMP_STALL_WM_MASK … #define DPFC_RECOMP_TIMER_COUNT_MASK … #define DPFC_STATUS … #define ILK_DPFC_STATUS(fbc_id) … #define DPFC_INVAL_SEG_MASK … #define DPFC_COMP_SEG_MASK … #define DPFC_STATUS2 … #define ILK_DPFC_STATUS2(fbc_id) … #define DPFC_COMP_SEG_MASK_IVB … #define DPFC_FENCE_YOFF … #define ILK_DPFC_FENCE_YOFF(fbc_id) … #define DPFC_CHICKEN … #define ILK_DPFC_CHICKEN(fbc_id) … #define DPFC_HT_MODIFY … #define DPFC_NUKE_ON_ANY_MODIFICATION … #define DPFC_CHICKEN_COMP_DUMMY_PIXEL … #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION … #define DPFC_DISABLE_DUMMY0 … #define GLK_FBC_STRIDE(fbc_id) … #define FBC_STRIDE_OVERRIDE … #define FBC_STRIDE_MASK … #define FBC_STRIDE(x) … #define ILK_FBC_RT_BASE … #define ILK_FBC_RT_VALID … #define SNB_FBC_FRONT_BUFFER … #define SNB_DPFC_CTL_SA … #define SNB_DPFC_FENCE_EN … #define SNB_DPFC_FENCENO_MASK … #define SNB_DPFC_FENCENO(fence) … #define SNB_DPFC_CPU_FENCE_OFFSET … #define IVB_FBC_RT_BASE … #define IVB_FBC_RT_BASE_UPPER … #define MSG_FBC_REND_STATE(fbc_id) … #define FBC_REND_NUKE … #define FBC_REND_CACHE_CLEAN … #endif /* __INTEL_FBC_REGS__ */
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