/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Copyright Fiona Klute <[email protected]> */ #ifndef __RTW8703B_H__ #define __RTW8703B_H__ #include "rtw8723x.h" extern const struct rtw_chip_info rtw8703b_hw_spec; /* phy status parsing */ #define VGA_BITS … #define LNA_L_BITS … #define LNA_H_BIT … /* masks for assembling LNA index from high and low bits */ #define BIT_LNA_H_MASK … #define BIT_LNA_L_MASK … struct phy_rx_agc_info { … } __packed; /* This struct is called phy_status_rpt_8192cd in the vendor driver, * there might be potential to share it with drivers for other chips * of the same generation. */ struct phy_status_8703b { … } __packed; /* Baseband registers */ #define REG_BB_PWR_SAV5_11N … /* BIT(11) should be 1 for 8703B *and* 8723D, which means LNA uses 4 * bit for CCK rates in report, not 3. Vendor driver logs a warning if * it's 0, but handles the case. * * Purpose of other parts of this register is unknown, 8723cs driver * code indicates some other chips use certain bits for antenna * diversity. */ #define REG_BB_AMP … #define BIT_MASK_RX_LNA … /* 0xaXX: 40MHz channel settings */ #define REG_CCK_TXSF2 … #define REG_CCK_DBG … #define REG_OFDM0_A_TX_AFE … #define REG_TXIQK_MATRIXB_LSB2_11N … #define REG_OFDM0_TX_PSD_NOISE … #define REG_IQK_RDY … /* RF registers */ #define RF_RCK1 … #define AGG_BURST_NUM … #define AGG_BURST_SIZE … #define BIT_MASK_AGG_BURST_NUM … #define BIT_MASK_AGG_BURST_SIZE … #endif /* __RTW8703B_H__ */
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