// SPDX-License-Identifier: GPL-2.0-or-later /* * Clock control for Cirrus EP93xx chips. * Copyright (C) 2021 Nikita Shubin <[email protected]> * * Based on a rewrite of arch/arm/mach-ep93xx/clock.c: * Copyright (C) 2006 Lennert Buytenhek <[email protected]> */ #define pr_fmt(fmt) … #include <linux/bits.h> #include <linux/cleanup.h> #include <linux/clk-provider.h> #include <linux/math.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/spinlock.h> #include <linux/soc/cirrus/ep93xx.h> #include <dt-bindings/clock/cirrus,ep9301-syscon.h> #include <asm/div64.h> #define EP93XX_EXT_CLK_RATE … #define EP93XX_EXT_RTC_RATE … #define EP93XX_SYSCON_POWER_STATE … #define EP93XX_SYSCON_PWRCNT … #define EP93XX_SYSCON_PWRCNT_UARTBAUD … #define EP93XX_SYSCON_PWRCNT_USH_EN … #define EP93XX_SYSCON_PWRCNT_DMA_M2M1 … #define EP93XX_SYSCON_PWRCNT_DMA_M2M0 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P8 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P9 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P6 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P7 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P4 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P5 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P2 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P3 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P0 … #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 … #define EP93XX_SYSCON_CLKSET1 … #define EP93XX_SYSCON_CLKSET1_NBYP1 … #define EP93XX_SYSCON_CLKSET2 … #define EP93XX_SYSCON_CLKSET2_NBYP2 … #define EP93XX_SYSCON_CLKSET2_PLL2_EN … #define EP93XX_SYSCON_DEVCFG … #define EP93XX_SYSCON_DEVCFG_U3EN … #define EP93XX_SYSCON_DEVCFG_U2EN … #define EP93XX_SYSCON_DEVCFG_U1EN … #define EP93XX_SYSCON_VIDCLKDIV … #define EP93XX_SYSCON_CLKDIV_ENABLE … #define EP93XX_SYSCON_CLKDIV_ESEL … #define EP93XX_SYSCON_CLKDIV_PSEL … #define EP93XX_SYSCON_CLKDIV_MASK … #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT … #define EP93XX_SYSCON_I2SCLKDIV … #define EP93XX_SYSCON_I2SCLKDIV_SENA … #define EP93XX_SYSCON_I2SCLKDIV_ORIDE … #define EP93XX_SYSCON_I2SCLKDIV_SPOL … #define EP93XX_SYSCON_KEYTCHCLKDIV … #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN … #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV … #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN … #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV … #define EP93XX_SYSCON_CHIPID … #define EP93XX_SYSCON_CHIPID_ID … #define EP93XX_FIXED_CLK_COUNT … static const char ep93xx_adc_divisors[] = …; static const char ep93xx_sclk_divisors[] = …; static const char ep93xx_lrclk_divisors[] = …; struct ep93xx_clk { … }; struct ep93xx_clk_priv { … }; static struct ep93xx_clk *ep93xx_clk_from(struct clk_hw *hw) { … } static struct ep93xx_clk_priv *ep93xx_priv_from(struct ep93xx_clk *clk) { … } static void ep93xx_clk_write(struct ep93xx_clk_priv *priv, unsigned int reg, unsigned int val) { … } static int ep93xx_clk_is_enabled(struct clk_hw *hw) { … } static int ep93xx_clk_enable(struct clk_hw *hw) { … } static void ep93xx_clk_disable(struct clk_hw *hw) { … } static const struct clk_ops clk_ep93xx_gate_ops = …; static int ep93xx_clk_register_gate(struct ep93xx_clk *clk, const char *name, struct clk_parent_data *parent_data, unsigned long flags, unsigned int reg, u8 bit_idx) { … } static u8 ep93xx_mux_get_parent(struct clk_hw *hw) { … } static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) { … } static bool is_best(unsigned long rate, unsigned long now, unsigned long best) { … } static int ep93xx_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops clk_ddiv_ops = …; static int ep93xx_clk_register_ddiv(struct ep93xx_clk *clk, const char *name, struct clk_parent_data *parent_data, u8 num_parents, unsigned int reg, u8 bit_idx) { … } static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops ep93xx_div_ops = …; static int ep93xx_register_div(struct ep93xx_clk *clk, const char *name, const struct clk_parent_data *parent_data, unsigned int reg, u8 enable_bit, u8 shift, u8 width, const char *clk_divisors, u8 num_div) { … } struct ep93xx_gate { … }; static const struct ep93xx_gate ep93xx_uarts[] = …; static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv) { … } static const struct ep93xx_gate ep93xx_dmas[] = …; static int ep93xx_dma_clock_init(struct ep93xx_clk_priv *priv) { … } static struct clk_hw *of_clk_ep93xx_get(struct of_phandle_args *clkspec, void *data) { … } /* * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS */ static unsigned long calc_pll_rate(u64 rate, u32 config_word) { … } static int ep93xx_plls_init(struct ep93xx_clk_priv *priv) { … } static int ep93xx_clk_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) { … } static const struct auxiliary_device_id ep93xx_clk_ids[] = …; MODULE_DEVICE_TABLE(auxiliary, ep93xx_clk_ids); static struct auxiliary_driver ep93xx_clk_driver = …; module_auxiliary_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
Codebase Browser
linux