// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/V2H(P) Clock Pulse Generator * * Copyright (C) 2024 Renesas Electronics Corp. * * Based on rzg2l-cpg.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2013 Ideas On Board SPRL * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/iopoll.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> #include <linux/reset-controller.h> #include <dt-bindings/clock/renesas-cpg-mssr.h> #include "rzv2h-cpg.h" #ifdef DEBUG #define WARN_DEBUG … #else #define WARN_DEBUG(x) … #endif #define GET_CLK_ON_OFFSET(x) … #define GET_CLK_MON_OFFSET(x) … #define GET_RST_OFFSET(x) … #define GET_RST_MON_OFFSET(x) … #define KDIV(val) … #define MDIV(val) … #define PDIV(val) … #define SDIV(val) … #define DDIV_DIVCTL_WEN(shift) … #define GET_MOD_CLK_ID(base, index, bit) … #define CPG_CLKSTATUS0 … /** * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data * * @dev: CPG device * @base: CPG register block base address * @rmw_lock: protects register accesses * @clks: Array containing all Core and Module Clocks * @num_core_clks: Number of Core Clocks in clks[] * @num_mod_clks: Number of Module Clocks in clks[] * @resets: Array of resets * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @rcdev: Reset controller entity */ struct rzv2h_cpg_priv { … }; #define rcdev_to_priv(x) … struct pll_clk { … }; #define to_pll(_hw) … /** * struct mod_clock - Module clock * * @priv: CPG private data * @hw: handle between common and hardware-specific interfaces * @on_index: register offset * @on_bit: ON/MON bit * @mon_index: monitor register offset * @mon_bit: montor bit */ struct mod_clock { … }; #define to_mod_clock(_hw) … /** * struct ddiv_clk - DDIV clock * * @priv: CPG private data * @div: divider clk * @mon: monitor bit in CPG_CLKSTATUS0 register */ struct ddiv_clk { … }; #define to_ddiv_clock(_div) … static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static const struct clk_ops rzv2h_cpg_pll_ops = …; static struct clk * __init rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv, const struct clk_ops *ops) { … } static unsigned long rzv2h_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long rzv2h_ddiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int rzv2h_ddiv_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { … } static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon) { … } static int rzv2h_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops rzv2h_ddiv_clk_divider_ops = …; static struct clk * __init rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { … } static struct clk *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) { … } static void __init rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv) { … } static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) { … } static int rzv2h_mod_clock_enable(struct clk_hw *hw) { … } static void rzv2h_mod_clock_disable(struct clk_hw *hw) { … } static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops rzv2h_mod_clock_ops = …; static void __init rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, struct rzv2h_cpg_priv *priv) { … } static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev, unsigned long id) { … } static int rzv2h_cpg_status(struct reset_controller_dev *rcdev, unsigned long id) { … } static const struct reset_control_ops rzv2h_cpg_reset_ops = …; static int rzv2h_cpg_reset_xlate(struct reset_controller_dev *rcdev, const struct of_phandle_args *reset_spec) { … } static int rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv *priv) { … } /** * struct rzv2h_cpg_pd - RZ/V2H power domain data structure * @priv: pointer to CPG private data structure * @genpd: generic PM domain */ struct rzv2h_cpg_pd { … }; static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev) { … } static void rzv2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev) { … } static void rzv2h_cpg_genpd_remove_simple(void *data) { … } static int __init rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv *priv) { … } static void rzv2h_cpg_del_clk_provider(void *data) { … } static int __init rzv2h_cpg_probe(struct platform_device *pdev) { … } static const struct of_device_id rzv2h_cpg_match[] = …; static struct platform_driver rzv2h_cpg_driver = …; static int __init rzv2h_cpg_init(void) { … } subsys_initcall(rzv2h_cpg_init); MODULE_DESCRIPTION(…) …;
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