/* SPDX-License-Identifier: GPL-2.0 */ /* * Renesas RZ/V2H(P) Clock Pulse Generator * * Copyright (C) 2024 Renesas Electronics Corp. */ #ifndef __RENESAS_RZV2H_CPG_H__ #define __RENESAS_RZV2H_CPG_H__ /** * struct ddiv - Structure for dynamic switching divider * * @offset: register offset * @shift: position of the divider bit * @width: width of the divider * @monbit: monitor bit in CPG_CLKSTATUS0 register */ struct ddiv { … }; #define DDIV_PACK(_offset, _shift, _width, _monbit) … #define CPG_CDDIV0 … #define CDDIV0_DIVCTL2 … /** * Definitions of CPG Core Clocks * * These include: * - Clock outputs exported to DT * - External input clocks * - Internal CPG clocks */ struct cpg_core_clk { … }; enum clk_types { … }; /* BIT(31) indicates if CLK1/2 are accessible or not */ #define PLL_CONF(n) … #define PLL_CLK_ACCESS(n) … #define PLL_CLK1_OFFSET(n) … #define PLL_CLK2_OFFSET(n) … #define DEF_TYPE(_name, _id, _type...) … #define DEF_BASE(_name, _id, _type, _parent...) … #define DEF_PLL(_name, _id, _parent, _conf) … #define DEF_INPUT(_name, _id) … #define DEF_FIXED(_name, _id, _parent, _mult, _div) … #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) … /** * struct rzv2h_mod_clk - Module Clocks definitions * * @name: handle between common and hardware-specific interfaces * @parent: id of parent clock * @critical: flag to indicate the clock is critical * @on_index: control register index * @on_bit: ON bit * @mon_index: monitor register index * @mon_bit: monitor bit */ struct rzv2h_mod_clk { … }; #define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) … #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) … #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) … /** * struct rzv2h_reset - Reset definitions * * @reset_index: reset register index * @reset_bit: reset bit * @mon_index: monitor register index * @mon_bit: monitor bit */ struct rzv2h_reset { … }; #define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) … #define DEF_RST(_resindex, _resbit, _monindex, _monbit) … /** * struct rzv2h_cpg_info - SoC-specific CPG Description * * @core_clks: Array of Core Clock definitions * @num_core_clks: Number of entries in core_clks[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @num_total_core_clks: Total number of Core Clocks (exported + internal) * * @mod_clks: Array of Module Clock definitions * @num_mod_clks: Number of entries in mod_clks[] * @num_hw_mod_clks: Number of Module Clocks supported by the hardware * * @resets: Array of Module Reset definitions * @num_resets: Number of entries in resets[] */ struct rzv2h_cpg_info { … }; extern const struct rzv2h_cpg_info r9a09g057_cpg_info; #endif /* __RENESAS_RZV2H_CPG_H__ */
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