// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2024 Samsung Electronics Co., Ltd. * Author: Sunyeal Hong <[email protected]> * * Common Clock Framework support for ExynosAuto v920 SoC. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/samsung,exynosautov920.h> #include "clk.h" #include "clk-exynos-arm64.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP … #define CLKS_NR_PERIC0 … /* ---- CMU_TOP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_TOP (0x11000000) */ #define PLL_LOCKTIME_PLL_MMC … #define PLL_LOCKTIME_PLL_SHARED0 … #define PLL_LOCKTIME_PLL_SHARED1 … #define PLL_LOCKTIME_PLL_SHARED2 … #define PLL_LOCKTIME_PLL_SHARED3 … #define PLL_LOCKTIME_PLL_SHARED4 … #define PLL_LOCKTIME_PLL_SHARED5 … #define PLL_CON0_PLL_MMC … #define PLL_CON3_PLL_MMC … #define PLL_CON0_PLL_SHARED0 … #define PLL_CON3_PLL_SHARED0 … #define PLL_CON0_PLL_SHARED1 … #define PLL_CON3_PLL_SHARED1 … #define PLL_CON0_PLL_SHARED2 … #define PLL_CON3_PLL_SHARED2 … #define PLL_CON0_PLL_SHARED3 … #define PLL_CON3_PLL_SHARED3 … #define PLL_CON0_PLL_SHARED4 … #define PLL_CON3_PLL_SHARED4 … #define PLL_CON0_PLL_SHARED5 … #define PLL_CON3_PLL_SHARED5 … /* MUX */ #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC … #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC … #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU … #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC … #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 … #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 … #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER … #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC … #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC … #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC … #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC … #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM … #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC … #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC … #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC … #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC … #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC … #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP … #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC … #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC … #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB … #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA … #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD … #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC … #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS … #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD … #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC … #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG … #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC … #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC … #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD … #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC … #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP … #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH … #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC … #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC … #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC … #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC … #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP … #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC … #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP … #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC … #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC … #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC … #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC … #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC … #define CLK_CON_MUX_MUX_CLK_CMU_NOCP … #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT … #define CLK_CON_MUX_MUX_CMU_CMUREF … /* DIV */ #define CLK_CON_DIV_CLKCMU_ACC_NOC … #define CLK_CON_DIV_CLKCMU_APM_NOC … #define CLK_CON_DIV_CLKCMU_AUD_CPU … #define CLK_CON_DIV_CLKCMU_AUD_NOC … #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 … #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 … #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 … #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 … #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER … #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG … #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH … #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER … #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH … #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER … #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH … #define CLK_CON_DIV_CLKCMU_DNC_NOC … #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC … #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC … #define CLK_CON_DIV_CLKCMU_DPTX_NOC … #define CLK_CON_DIV_CLKCMU_DPUB_DSIM … #define CLK_CON_DIV_CLKCMU_DPUB_NOC … #define CLK_CON_DIV_CLKCMU_DPUF0_NOC … #define CLK_CON_DIV_CLKCMU_DPUF1_NOC … #define CLK_CON_DIV_CLKCMU_DPUF2_NOC … #define CLK_CON_DIV_CLKCMU_DSP_NOC … #define CLK_CON_DIV_CLKCMU_G3D_NOCP … #define CLK_CON_DIV_CLKCMU_G3D_SWITCH … #define CLK_CON_DIV_CLKCMU_GNPU_NOC … #define CLK_CON_DIV_CLKCMU_HSI0_NOC … #define CLK_CON_DIV_CLKCMU_ACC_ORB … #define CLK_CON_DIV_CLKCMU_GNPU_XMAA … #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD … #define CLK_CON_DIV_CLKCMU_HSI1_NOC … #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD … #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET … #define CLK_CON_DIV_CLKCMU_HSI2_NOC … #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS … #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD … #define CLK_CON_DIV_CLKCMU_ISP_NOC … #define CLK_CON_DIV_CLKCMU_M2M_JPEG … #define CLK_CON_DIV_CLKCMU_M2M_NOC … #define CLK_CON_DIV_CLKCMU_MFC_MFC … #define CLK_CON_DIV_CLKCMU_MFC_WFD … #define CLK_CON_DIV_CLKCMU_MFD_NOC … #define CLK_CON_DIV_CLKCMU_MIF_NOCP … #define CLK_CON_DIV_CLKCMU_MISC_NOC … #define CLK_CON_DIV_CLKCMU_NOCL0_NOC … #define CLK_CON_DIV_CLKCMU_NOCL1_NOC … #define CLK_CON_DIV_CLKCMU_NOCL2_NOC … #define CLK_CON_DIV_CLKCMU_PERIC0_IP … #define CLK_CON_DIV_CLKCMU_PERIC0_NOC … #define CLK_CON_DIV_CLKCMU_PERIC1_IP … #define CLK_CON_DIV_CLKCMU_PERIC1_NOC … #define CLK_CON_DIV_CLKCMU_SDMA_NOC … #define CLK_CON_DIV_CLKCMU_SNW_NOC … #define CLK_CON_DIV_CLKCMU_SSP_NOC … #define CLK_CON_DIV_CLKCMU_TAA_NOC … #define CLK_CON_DIV_CLK_ADD_CH_CLK … #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT … #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST … #define CLK_CON_DIV_DIV_CLK_CMU_NOCP … static const unsigned long top_clk_regs[] __initconst = …; static const struct samsung_pll_clock top_pll_clks[] __initconst = …; /* List of parent clocks for Muxes in CMU_TOP */ PNAME(mout_shared0_pll_p) = …; PNAME(mout_shared1_pll_p) = …; PNAME(mout_shared2_pll_p) = …; PNAME(mout_shared3_pll_p) = …; PNAME(mout_shared4_pll_p) = …; PNAME(mout_shared5_pll_p) = …; PNAME(mout_mmc_pll_p) = …; PNAME(mout_clkcmu_cmu_boost_p) = …; PNAME(mout_clkcmu_cmu_cmuref_p) = …; PNAME(mout_clkcmu_acc_noc_p) = …; PNAME(mout_clkcmu_acc_orb_p) = …; PNAME(mout_clkcmu_apm_noc_p) = …; PNAME(mout_clkcmu_aud_cpu_p) = …; PNAME(mout_clkcmu_aud_noc_p) = …; PNAME(mout_clkcmu_cpucl0_switch_p) = …; PNAME(mout_clkcmu_cpucl0_cluster_p) = …; PNAME(mout_clkcmu_cpucl0_dbg_p) = …; PNAME(mout_clkcmu_cpucl1_switch_p) = …; PNAME(mout_clkcmu_cpucl1_cluster_p) = …; PNAME(mout_clkcmu_cpucl2_switch_p) = …; PNAME(mout_clkcmu_cpucl2_cluster_p) = …; PNAME(mout_clkcmu_dnc_noc_p) = …; PNAME(mout_clkcmu_dptx_noc_p) = …; PNAME(mout_clkcmu_dptx_dpgtc_p) = …; PNAME(mout_clkcmu_dptx_dposc_p) = …; PNAME(mout_clkcmu_dpub_noc_p) = …; PNAME(mout_clkcmu_dpub_dsim_p) = …; PNAME(mout_clkcmu_dpuf_noc_p) = …; PNAME(mout_clkcmu_dsp_noc_p) = …; PNAME(mout_clkcmu_g3d_switch_p) = …; PNAME(mout_clkcmu_g3d_nocp_p) = …; PNAME(mout_clkcmu_gnpu_noc_p) = …; PNAME(mout_clkcmu_hsi0_noc_p) = …; PNAME(mout_clkcmu_hsi1_noc_p) = …; PNAME(mout_clkcmu_hsi1_usbdrd_p) = …; PNAME(mout_clkcmu_hsi1_mmc_card_p) = …; PNAME(mout_clkcmu_hsi2_noc_p) = …; PNAME(mout_clkcmu_hsi2_noc_ufs_p) = …; PNAME(mout_clkcmu_hsi2_ufs_embd_p) = …; PNAME(mout_clkcmu_hsi2_ethernet_p) = …; PNAME(mout_clkcmu_isp_noc_p) = …; PNAME(mout_clkcmu_m2m_noc_p) = …; PNAME(mout_clkcmu_m2m_jpeg_p) = …; PNAME(mout_clkcmu_mfc_mfc_p) = …; PNAME(mout_clkcmu_mfc_wfd_p) = …; PNAME(mout_clkcmu_mfd_noc_p) = …; PNAME(mout_clkcmu_mif_switch_p) = …; PNAME(mout_clkcmu_mif_nocp_p) = …; PNAME(mout_clkcmu_misc_noc_p) = …; PNAME(mout_clkcmu_nocl0_noc_p) = …; PNAME(mout_clkcmu_nocl1_noc_p) = …; PNAME(mout_clkcmu_nocl2_noc_p) = …; PNAME(mout_clkcmu_peric0_noc_p) = …; PNAME(mout_clkcmu_peric0_ip_p) = …; PNAME(mout_clkcmu_peric1_noc_p) = …; PNAME(mout_clkcmu_peric1_ip_p) = …; PNAME(mout_clkcmu_sdma_noc_p) = …; PNAME(mout_clkcmu_snw_noc_p) = …; PNAME(mout_clkcmu_ssp_noc_p) = …; PNAME(mout_clkcmu_taa_noc_p) = …; static const struct samsung_mux_clock top_mux_clks[] __initconst = …; static const struct samsung_div_clock top_div_clks[] __initconst = …; static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = …; static const struct samsung_cmu_info top_cmu_info __initconst = …; static void __init exynosautov920_cmu_top_init(struct device_node *np) { … } /* Register CMU_TOP early, as it's a dependency for other early domains */ CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top", exynosautov920_cmu_top_init); /* ---- CMU_PERIC0 --------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER … #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER … #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI … #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C … #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI … #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C … static const unsigned long peric0_clk_regs[] __initconst = …; /* List of parent clocks for Muxes in CMU_PERIC0 */ PNAME(mout_peric0_ip_user_p) = …; PNAME(mout_peric0_noc_user_p) = …; PNAME(mout_peric0_usi_p) = …; static const struct samsung_mux_clock peric0_mux_clks[] __initconst = …; static const struct samsung_div_clock peric0_div_clks[] __initconst = …; static const struct samsung_cmu_info peric0_cmu_info __initconst = …; static int __init exynosautov920_cmu_probe(struct platform_device *pdev) { … } static const struct of_device_id exynosautov920_cmu_of_match[] = …; static struct platform_driver exynosautov920_cmu_driver __refdata = …; static int __init exynosautov920_cmu_init(void) { … } core_initcall(exynosautov920_cmu_init);
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