// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) KEBA Industrial Automation Gmbh 2024 * * Driver for KEBA I2C controller FPGA IP core */ #include <linux/i2c.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/misc/keba.h> #define KI2C … #define KI2C_CAPABILITY_REG … #define KI2C_CAPABILITY_CRYPTO … #define KI2C_CAPABILITY_DC … #define KI2C_CONTROL_REG … #define KI2C_CONTROL_MEN … #define KI2C_CONTROL_MSTA … #define KI2C_CONTROL_RSTA … #define KI2C_CONTROL_MTX … #define KI2C_CONTROL_TXAK … #define KI2C_CONTROL_DISABLE … #define KI2C_CONTROL_DC_REG … #define KI2C_CONTROL_DC_SDA … #define KI2C_CONTROL_DC_SCL … #define KI2C_STATUS_REG … #define KI2C_STATUS_IN_USE … #define KI2C_STATUS_ACK_CYC … #define KI2C_STATUS_RXAK … #define KI2C_STATUS_MCF … #define KI2C_STATUS_DC_REG … #define KI2C_STATUS_DC_SDA … #define KI2C_STATUS_DC_SCL … #define KI2C_DATA_REG … #define KI2C_INUSE_SLEEP_US … #define KI2C_INUSE_TIMEOUT_US … #define KI2C_POLL_DELAY_US … struct ki2c { … }; static int ki2c_inuse_lock(struct ki2c *ki2c) { … } static void ki2c_inuse_unlock(struct ki2c *ki2c) { … } static int ki2c_wait_for_bit(void __iomem *addr, u8 mask, unsigned long timeout) { … } static int ki2c_wait_for_mcf(struct ki2c *ki2c) { … } static int ki2c_wait_for_data(struct ki2c *ki2c) { … } static int ki2c_wait_for_data_ack(struct ki2c *ki2c) { … } static int ki2c_has_capability(struct ki2c *ki2c, unsigned int cap) { … } static int ki2c_get_scl(struct ki2c *ki2c) { … } static int ki2c_get_sda(struct ki2c *ki2c) { … } static void ki2c_set_scl(struct ki2c *ki2c, int val) { … } /* * Resetting bus bitwise is done by checking SDA and applying clock cycles as * long as SDA is low. 9 clock cycles are applied at most. * * Clock cycles are generated and udelay() determines the duration of clock * cycles. Generated clock rate is 100 KHz and so duration of both clock levels * is: delay in ns = (10^6 / 100) / 2 */ #define KI2C_RECOVERY_CLK_CNT … #define KI2C_RECOVERY_UDELAY … static int ki2c_reset_bus_bitwise(struct ki2c *ki2c) { … } /* * Resetting bus bytewise is done by writing start bit, 9 data bits and stop * bit. * * This is not 100% safe. If target is an EEPROM and a write access was * interrupted during the ACK cycle, this approach might not be able to recover * the bus. The reason is, that after the 9 clock cycles the EEPROM will be in * ACK cycle again and will hold SDA low like it did before the start of the * routine. Furthermore the EEPROM might get written one additional byte with * 0xff into it. Thus, use bitwise approach whenever possible, especially when * EEPROMs are on the bus. */ static int ki2c_reset_bus_bytewise(struct ki2c *ki2c) { … } static int ki2c_reset_bus(struct ki2c *ki2c) { … } static void ki2c_write_target_addr(struct ki2c *ki2c, struct i2c_msg *m) { … } static int ki2c_start_addr(struct ki2c *ki2c, struct i2c_msg *m) { … } static int ki2c_repstart_addr(struct ki2c *ki2c, struct i2c_msg *m) { … } static void ki2c_stop(struct ki2c *ki2c) { … } static int ki2c_write(struct ki2c *ki2c, const u8 *data, int len) { … } static int ki2c_read(struct ki2c *ki2c, u8 *data, int len) { … } static int ki2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { … } static void ki2c_unregister_devices(struct ki2c *ki2c) { … } static int ki2c_register_devices(struct ki2c *ki2c) { … } static u32 ki2c_func(struct i2c_adapter *adap) { … } static const struct i2c_algorithm ki2c_algo = …; static int ki2c_probe(struct auxiliary_device *auxdev, const struct auxiliary_device_id *id) { … } static void ki2c_remove(struct auxiliary_device *auxdev) { … } static const struct auxiliary_device_id ki2c_devtype_aux[] = …; MODULE_DEVICE_TABLE(auxiliary, ki2c_devtype_aux); static struct auxiliary_driver ki2c_driver_aux = …; module_auxiliary_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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