// SPDX-License-Identifier: GPL-2.0-only /* * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips * * https://www.analog.com/en/products/ad4695.html * https://www.analog.com/en/products/ad4696.html * https://www.analog.com/en/products/ad4697.html * https://www.analog.com/en/products/ad4698.html * * Copyright 2024 Analog Devices Inc. * Copyright 2024 BayLibre, SAS */ #include <linux/align.h> #include <linux/bitfield.h> #include <linux/bits.h> #include <linux/compiler.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> #include <linux/gpio/consumer.h> #include <linux/iio/buffer.h> #include <linux/iio/iio.h> #include <linux/iio/triggered_buffer.h> #include <linux/iio/trigger_consumer.h> #include <linux/minmax.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/spi/spi.h> #include <linux/units.h> #include <dt-bindings/iio/adi,ad4695.h> /* AD4695 registers */ #define AD4695_REG_SPI_CONFIG_A … #define AD4695_REG_SPI_CONFIG_A_SW_RST … #define AD4695_REG_SPI_CONFIG_A_ADDR_DIR … #define AD4695_REG_SPI_CONFIG_B … #define AD4695_REG_SPI_CONFIG_B_INST_MODE … #define AD4695_REG_DEVICE_TYPE … #define AD4695_REG_SCRATCH_PAD … #define AD4695_REG_VENDOR_L … #define AD4695_REG_VENDOR_H … #define AD4695_REG_LOOP_MODE … #define AD4695_REG_SPI_CONFIG_C … #define AD4695_REG_SPI_CONFIG_C_MB_STRICT … #define AD4695_REG_SPI_STATUS … #define AD4695_REG_STATUS … #define AD4695_REG_ALERT_STATUS1 … #define AD4695_REG_ALERT_STATUS2 … #define AD4695_REG_CLAMP_STATUS … #define AD4695_REG_SETUP … #define AD4695_REG_SETUP_LDO_EN … #define AD4695_REG_SETUP_SPI_MODE … #define AD4695_REG_SETUP_SPI_CYC_CTRL … #define AD4695_REG_REF_CTRL … #define AD4695_REG_REF_CTRL_OV_MODE … #define AD4695_REG_REF_CTRL_VREF_SET … #define AD4695_REG_REF_CTRL_REFHIZ_EN … #define AD4695_REG_REF_CTRL_REFBUF_EN … #define AD4695_REG_SEQ_CTRL … #define AD4695_REG_SEQ_CTRL_STD_SEQ_EN … #define AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS … #define AD4695_REG_AC_CTRL … #define AD4695_REG_STD_SEQ_CONFIG … #define AD4695_REG_GPIO_CTRL … #define AD4695_REG_GP_MODE … #define AD4695_REG_TEMP_CTRL … #define AD4695_REG_TEMP_CTRL_TEMP_EN … #define AD4695_REG_CONFIG_IN(n) … #define AD4695_REG_CONFIG_IN_MODE … #define AD4695_REG_CONFIG_IN_PAIR … #define AD4695_REG_CONFIG_IN_AINHIGHZ_EN … #define AD4695_REG_UPPER_IN(n) … #define AD4695_REG_LOWER_IN(n) … #define AD4695_REG_HYST_IN(n) … #define AD4695_REG_OFFSET_IN(n) … #define AD4695_REG_GAIN_IN(n) … #define AD4695_REG_AS_SLOT(n) … #define AD4695_REG_AS_SLOT_INX … /* Conversion mode commands */ #define AD4695_CMD_EXIT_CNV_MODE … #define AD4695_CMD_TEMP_CHAN … #define AD4695_CMD_VOLTAGE_CHAN(n) … /* timing specs */ #define AD4695_T_CONVERT_NS … #define AD4695_T_WAKEUP_HW_MS … #define AD4695_T_WAKEUP_SW_MS … #define AD4695_T_REFBUF_MS … #define AD4695_T_REGCONFIG_NS … #define AD4695_REG_ACCESS_SCLK_HZ … /* Max number of voltage input channels. */ #define AD4695_MAX_CHANNELS … /* Max size of 1 raw sample in bytes. */ #define AD4695_MAX_CHANNEL_SIZE … enum ad4695_in_pair { … }; struct ad4695_chip_info { … }; struct ad4695_channel_config { … }; struct ad4695_state { … }; static const struct regmap_range ad4695_regmap_rd_ranges[] = …; static const struct regmap_access_table ad4695_regmap_rd_table = …; static const struct regmap_range ad4695_regmap_wr_ranges[] = …; static const struct regmap_access_table ad4695_regmap_wr_table = …; static const struct regmap_config ad4695_regmap_config = …; static const struct regmap_range ad4695_regmap16_rd_ranges[] = …; static const struct regmap_access_table ad4695_regmap16_rd_table = …; static const struct regmap_range ad4695_regmap16_wr_ranges[] = …; static const struct regmap_access_table ad4695_regmap16_wr_table = …; static const struct regmap_config ad4695_regmap16_config = …; static const struct iio_chan_spec ad4695_channel_template = …; static const struct iio_chan_spec ad4695_temp_channel_template = …; static const struct iio_chan_spec ad4695_soft_timestamp_channel_template = …; static const char * const ad4695_power_supplies[] = …; static const struct ad4695_chip_info ad4695_chip_info = …; static const struct ad4695_chip_info ad4696_chip_info = …; static const struct ad4695_chip_info ad4697_chip_info = …; static const struct ad4695_chip_info ad4698_chip_info = …; /** * ad4695_set_single_cycle_mode - Set the device in single cycle mode * @st: The AD4695 state * @channel: The first channel to read * * As per the datasheet, to enable single cycle mode, we need to set * STD_SEQ_EN=0, NUM_SLOTS_AS=0 and CYC_CTRL=1 (Table 15). Setting SPI_MODE=1 * triggers the first conversion using the channel in AS_SLOT0. * * Context: can sleep, must be called with iio_device_claim_direct held * Return: 0 on success, a negative error code on failure */ static int ad4695_set_single_cycle_mode(struct ad4695_state *st, unsigned int channel) { … } /** * ad4695_enter_advanced_sequencer_mode - Put the ADC in advanced sequencer mode * @st: The driver state * @n: The number of slots to use - must be >= 2, <= 128 * * As per the datasheet, to enable advanced sequencer, we need to set * STD_SEQ_EN=0, NUM_SLOTS_AS=n-1 and CYC_CTRL=0 (Table 15). Setting SPI_MODE=1 * triggers the first conversion using the channel in AS_SLOT0. * * Return: 0 on success, a negative error code on failure */ static int ad4695_enter_advanced_sequencer_mode(struct ad4695_state *st, u32 n) { … } /** * ad4695_exit_conversion_mode - Exit conversion mode * @st: The AD4695 state * * Sends SPI command to exit conversion mode. * * Return: 0 on success, a negative error code on failure */ static int ad4695_exit_conversion_mode(struct ad4695_state *st) { … } static int ad4695_set_ref_voltage(struct ad4695_state *st, int vref_mv) { … } static int ad4695_write_chn_cfg(struct ad4695_state *st, struct ad4695_channel_config *cfg) { … } static int ad4695_buffer_preenable(struct iio_dev *indio_dev) { … } static int ad4695_buffer_postdisable(struct iio_dev *indio_dev) { … } static const struct iio_buffer_setup_ops ad4695_buffer_setup_ops = …; static irqreturn_t ad4695_trigger_handler(int irq, void *p) { … } /** * ad4695_read_one_sample - Read a single sample using single-cycle mode * @st: The AD4695 state * @address: The address of the channel to read * * Upon successful return, the sample will be stored in `st->raw_data`. * * Context: can sleep, must be called with iio_device_claim_direct held * Return: 0 on success, a negative error code on failure */ static int ad4695_read_one_sample(struct ad4695_state *st, unsigned int address) { … } static int ad4695_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { … } static int ad4695_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { … } static int ad4695_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, const int **vals, int *type, int *length, long mask) { … } static int ad4695_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, unsigned int *readval) { … } static const struct iio_info ad4695_info = …; static int ad4695_parse_channel_cfg(struct ad4695_state *st) { … } static int ad4695_probe(struct spi_device *spi) { … } static const struct spi_device_id ad4695_spi_id_table[] = …; MODULE_DEVICE_TABLE(spi, ad4695_spi_id_table); static const struct of_device_id ad4695_of_match_table[] = …; MODULE_DEVICE_TABLE(of, ad4695_of_match_table); static struct spi_driver ad4695_driver = …; module_spi_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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