linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_bwc.h

/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */

#ifndef MLX5HWS_BWC_H_
#define MLX5HWS_BWC_H_

#define MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG …
#define MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP …
#define MLX5HWS_BWC_MATCHER_REHASH_PERCENT_TH …
#define MLX5HWS_BWC_MATCHER_REHASH_BURST_TH …
#define MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM …

#define MLX5HWS_BWC_MAX_ACTS …

struct mlx5hws_bwc_matcher { … };

struct mlx5hws_bwc_rule { … };

int
mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_matcher *bwc_matcher,
				  struct mlx5hws_table *table,
				  u32 priority,
				  u8 match_criteria_enable,
				  struct mlx5hws_match_parameters *mask,
				  enum mlx5hws_action_type action_types[]);

int mlx5hws_bwc_matcher_destroy_simple(struct mlx5hws_bwc_matcher *bwc_matcher);

struct mlx5hws_bwc_rule *mlx5hws_bwc_rule_alloc(struct mlx5hws_bwc_matcher *bwc_matcher);

void mlx5hws_bwc_rule_free(struct mlx5hws_bwc_rule *bwc_rule);

int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_rule *bwc_rule,
				   u32 *match_param,
				   struct mlx5hws_rule_action rule_actions[],
				   u32 flow_source,
				   u16 bwc_queue_idx);

int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_rule *bwc_rule);

void mlx5hws_bwc_rule_fill_attr(struct mlx5hws_bwc_matcher *bwc_matcher,
				u16 bwc_queue_idx,
				u32 flow_source,
				struct mlx5hws_rule_attr *rule_attr);

static inline u16 mlx5hws_bwc_queues(struct mlx5hws_context *ctx)
{ … }

static inline u16 mlx5hws_bwc_get_queue_id(struct mlx5hws_context *ctx, u16 idx)
{ … }

#endif /* MLX5HWS_BWC_H_ */