linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_definer.h

/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */

#ifndef MLX5HWS_DEFINER_H_
#define MLX5HWS_DEFINER_H_

/* Max available selecotrs */
#define DW_SELECTORS …
#define BYTE_SELECTORS …

/* Selectors based on match TAG */
#define DW_SELECTORS_MATCH …
#define DW_SELECTORS_LIMITED …

/* Selectors based on range TAG */
#define DW_SELECTORS_RANGE …
#define BYTE_SELECTORS_RANGE …

#define HWS_NUM_OF_FLEX_PARSERS …

enum mlx5hws_definer_fname { … };

enum mlx5hws_definer_match_criteria { … };

enum mlx5hws_definer_type { … };

enum mlx5hws_definer_match_flag { … };

struct mlx5hws_definer_fc { … };

struct mlx5_ifc_definer_hl_eth_l2_bits { … };

struct mlx5_ifc_definer_hl_eth_l2_src_bits { … };

struct mlx5_ifc_definer_hl_ib_l2_bits { … };

struct mlx5_ifc_definer_hl_eth_l3_bits { … };

struct mlx5_ifc_definer_hl_eth_l4_bits { … };

struct mlx5_ifc_definer_hl_src_qp_gvmi_bits { … };

struct mlx5_ifc_definer_hl_ib_l4_bits { … };

enum mlx5hws_integrity_ok1_bits { … };

struct mlx5_ifc_definer_hl_oks1_bits { … };

struct mlx5_ifc_definer_hl_oks2_bits { … };

struct mlx5_ifc_definer_hl_voq_bits { … };

struct mlx5_ifc_definer_hl_ipv4_src_dst_bits { … };

struct mlx5_ifc_definer_hl_random_number_bits { … };

struct mlx5_ifc_definer_hl_ipv6_addr_bits { … };

struct mlx5_ifc_definer_tcp_icmp_header_bits { … };

struct mlx5_ifc_definer_hl_tunnel_header_bits { … };

struct mlx5_ifc_definer_hl_ipsec_bits { … };

struct mlx5_ifc_definer_hl_metadata_bits { … };

struct mlx5_ifc_definer_hl_flex_parser_bits { … };

struct mlx5_ifc_definer_hl_registers_bits { … };

struct mlx5_ifc_definer_hl_mpls_bits { … };

struct mlx5_ifc_definer_hl_bits { … };

enum mlx5hws_definer_gtp { … };

struct mlx5_ifc_header_gtp_bits { … };

struct mlx5_ifc_header_opt_gtp_bits { … };

struct mlx5_ifc_header_gtp_psc_bits { … };

struct mlx5_ifc_header_ipv6_vtc_bits { … };

struct mlx5_ifc_header_ipv6_routing_ext_bits { … };

struct mlx5_ifc_header_vxlan_bits { … };

struct mlx5_ifc_header_vxlan_gpe_bits { … };

struct mlx5_ifc_header_gre_bits { … };

struct mlx5_ifc_header_geneve_bits { … };

struct mlx5_ifc_header_geneve_opt_bits { … };

struct mlx5_ifc_header_icmp_bits { … };

struct mlx5hws_definer { … };

struct mlx5hws_definer_cache { … };

struct mlx5hws_definer_cache_item { … };

static inline bool
mlx5hws_definer_is_jumbo(struct mlx5hws_definer *definer)
{ … }

void mlx5hws_definer_create_tag(u32 *match_param,
				struct mlx5hws_definer_fc *fc,
				u32 fc_sz,
				u8 *tag);

int mlx5hws_definer_get_id(struct mlx5hws_definer *definer);

int mlx5hws_definer_mt_init(struct mlx5hws_context *ctx,
			    struct mlx5hws_match_template *mt);

void mlx5hws_definer_mt_uninit(struct mlx5hws_context *ctx,
			       struct mlx5hws_match_template *mt);

int mlx5hws_definer_init_cache(struct mlx5hws_definer_cache **cache);

void mlx5hws_definer_uninit_cache(struct mlx5hws_definer_cache *cache);

int mlx5hws_definer_compare(struct mlx5hws_definer *definer_a,
			    struct mlx5hws_definer *definer_b);

int mlx5hws_definer_get_obj(struct mlx5hws_context *ctx,
			    struct mlx5hws_definer *definer);

void mlx5hws_definer_free(struct mlx5hws_context *ctx,
			  struct mlx5hws_definer *definer);

int mlx5hws_definer_calc_layout(struct mlx5hws_context *ctx,
				struct mlx5hws_match_template *mt,
				struct mlx5hws_definer *match_definer);

struct mlx5hws_definer_fc *
mlx5hws_definer_conv_match_params_to_compressed_fc(struct mlx5hws_context *ctx,
						   u8 match_criteria_enable,
						   u32 *match_param,
						   int *fc_sz);

#endif /* MLX5HWS_DEFINER_H_ */