// SPDX-License-Identifier: GPL-2.0+ /* * OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface framework * * Author: Parthiban Veerasooran <[email protected]> */ #include <linux/bitfield.h> #include <linux/iopoll.h> #include <linux/mdio.h> #include <linux/phy.h> #include <linux/oa_tc6.h> /* OPEN Alliance TC6 registers */ /* Standard Capabilities Register */ #define OA_TC6_REG_STDCAP … #define STDCAP_DIRECT_PHY_REG_ACCESS … /* Reset Control and Status Register */ #define OA_TC6_REG_RESET … #define RESET_SWRESET … /* Configuration Register #0 */ #define OA_TC6_REG_CONFIG0 … #define CONFIG0_SYNC … #define CONFIG0_ZARFE_ENABLE … /* Status Register #0 */ #define OA_TC6_REG_STATUS0 … #define STATUS0_RESETC … #define STATUS0_HEADER_ERROR … #define STATUS0_LOSS_OF_FRAME_ERROR … #define STATUS0_RX_BUFFER_OVERFLOW_ERROR … #define STATUS0_TX_PROTOCOL_ERROR … /* Buffer Status Register */ #define OA_TC6_REG_BUFFER_STATUS … #define BUFFER_STATUS_TX_CREDITS_AVAILABLE … #define BUFFER_STATUS_RX_CHUNKS_AVAILABLE … /* Interrupt Mask Register #0 */ #define OA_TC6_REG_INT_MASK0 … #define INT_MASK0_HEADER_ERR_MASK … #define INT_MASK0_LOSS_OF_FRAME_ERR_MASK … #define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK … #define INT_MASK0_TX_PROTOCOL_ERR_MASK … /* PHY Clause 22 registers base address and mask */ #define OA_TC6_PHY_STD_REG_ADDR_BASE … #define OA_TC6_PHY_STD_REG_ADDR_MASK … /* Control command header */ #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL … #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ … #define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR … #define OA_TC6_CTRL_HEADER_ADDR … #define OA_TC6_CTRL_HEADER_LENGTH … #define OA_TC6_CTRL_HEADER_PARITY … /* Data header */ #define OA_TC6_DATA_HEADER_DATA_NOT_CTRL … #define OA_TC6_DATA_HEADER_DATA_VALID … #define OA_TC6_DATA_HEADER_START_VALID … #define OA_TC6_DATA_HEADER_START_WORD_OFFSET … #define OA_TC6_DATA_HEADER_END_VALID … #define OA_TC6_DATA_HEADER_END_BYTE_OFFSET … #define OA_TC6_DATA_HEADER_PARITY … /* Data footer */ #define OA_TC6_DATA_FOOTER_EXTENDED_STS … #define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD … #define OA_TC6_DATA_FOOTER_CONFIG_SYNC … #define OA_TC6_DATA_FOOTER_RX_CHUNKS … #define OA_TC6_DATA_FOOTER_DATA_VALID … #define OA_TC6_DATA_FOOTER_START_VALID … #define OA_TC6_DATA_FOOTER_START_WORD_OFFSET … #define OA_TC6_DATA_FOOTER_END_VALID … #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET … #define OA_TC6_DATA_FOOTER_TX_CREDITS … /* PHY – Clause 45 registers memory map selector (MMS) as per table 6 in the * OPEN Alliance specification. */ #define OA_TC6_PHY_C45_PCS_MMS2 … #define OA_TC6_PHY_C45_PMA_PMD_MMS3 … #define OA_TC6_PHY_C45_VS_PLCA_MMS4 … #define OA_TC6_PHY_C45_AUTO_NEG_MMS5 … #define OA_TC6_PHY_C45_POWER_UNIT_MMS6 … #define OA_TC6_CTRL_HEADER_SIZE … #define OA_TC6_CTRL_REG_VALUE_SIZE … #define OA_TC6_CTRL_IGNORED_SIZE … #define OA_TC6_CTRL_MAX_REGISTERS … #define OA_TC6_CTRL_SPI_BUF_SIZE … #define OA_TC6_CHUNK_PAYLOAD_SIZE … #define OA_TC6_DATA_HEADER_SIZE … #define OA_TC6_CHUNK_SIZE … #define OA_TC6_MAX_TX_CHUNKS … #define OA_TC6_SPI_DATA_BUF_SIZE … #define STATUS0_RESETC_POLL_DELAY … #define STATUS0_RESETC_POLL_TIMEOUT … /* Internal structure for MAC-PHY drivers */ struct oa_tc6 { … }; enum oa_tc6_header_type { … }; enum oa_tc6_register_op { … }; enum oa_tc6_data_valid_info { … }; enum oa_tc6_data_start_valid_info { … }; enum oa_tc6_data_end_valid_info { … }; static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, enum oa_tc6_header_type header_type, u16 length) { … } static int oa_tc6_get_parity(u32 p) { … } static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, enum oa_tc6_register_op reg_op) { … } static void oa_tc6_update_ctrl_write_data(struct oa_tc6 *tc6, u32 value[], u8 length) { … } static u16 oa_tc6_calculate_ctrl_buf_size(u8 length) { … } static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length, enum oa_tc6_register_op reg_op) { … } static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size) { … } static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 size) { … } static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *tc6, u32 value[], u8 length) { … } static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length, enum oa_tc6_register_op reg_op) { … } /** * oa_tc6_read_registers - function for reading multiple consecutive registers. * @tc6: oa_tc6 struct. * @address: address of the first register to be read in the MAC-PHY. * @value: values to be read from the starting register address @address. * @length: number of consecutive registers to be read from @address. * * Maximum of 128 consecutive registers can be read starting at @address. * * Return: 0 on success otherwise failed. */ int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length) { … } EXPORT_SYMBOL_GPL(…); /** * oa_tc6_read_register - function for reading a MAC-PHY register. * @tc6: oa_tc6 struct. * @address: register address of the MAC-PHY to be read. * @value: value read from the @address register address of the MAC-PHY. * * Return: 0 on success otherwise failed. */ int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value) { … } EXPORT_SYMBOL_GPL(…); /** * oa_tc6_write_registers - function for writing multiple consecutive registers. * @tc6: oa_tc6 struct. * @address: address of the first register to be written in the MAC-PHY. * @value: values to be written from the starting register address @address. * @length: number of consecutive registers to be written from @address. * * Maximum of 128 consecutive registers can be written starting at @address. * * Return: 0 on success otherwise failed. */ int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], u8 length) { … } EXPORT_SYMBOL_GPL(…); /** * oa_tc6_write_register - function for writing a MAC-PHY register. * @tc6: oa_tc6 struct. * @address: register address of the MAC-PHY to be written. * @value: value to be written in the @address register address of the MAC-PHY. * * Return: 0 on success otherwise failed. */ int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value) { … } EXPORT_SYMBOL_GPL(…); static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6) { … } static void oa_tc6_handle_link_change(struct net_device *netdev) { … } static int oa_tc6_mdiobus_read(struct mii_bus *bus, int addr, int regnum) { … } static int oa_tc6_mdiobus_write(struct mii_bus *bus, int addr, int regnum, u16 val) { … } static int oa_tc6_get_phy_c45_mms(int devnum) { … } static int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum) { … } static int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) { … } static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) { … } static void oa_tc6_mdiobus_unregister(struct oa_tc6 *tc6) { … } static int oa_tc6_phy_init(struct oa_tc6 *tc6) { … } static void oa_tc6_phy_exit(struct oa_tc6 *tc6) { … } static int oa_tc6_read_status0(struct oa_tc6 *tc6) { … } static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) { … } static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) { … } static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6) { … } static void oa_tc6_cleanup_ongoing_rx_skb(struct oa_tc6 *tc6) { … } static void oa_tc6_cleanup_ongoing_tx_skb(struct oa_tc6 *tc6) { … } static int oa_tc6_process_extended_status(struct oa_tc6 *tc6) { … } static int oa_tc6_process_rx_chunk_footer(struct oa_tc6 *tc6, u32 footer) { … } static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) { … } static void oa_tc6_update_rx_skb(struct oa_tc6 *tc6, u8 *payload, u8 length) { … } static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6) { … } static int oa_tc6_prcs_complete_rx_frame(struct oa_tc6 *tc6, u8 *payload, u16 size) { … } static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16 size) { … } static void oa_tc6_prcs_rx_frame_end(struct oa_tc6 *tc6, u8 *payload, u16 size) { … } static void oa_tc6_prcs_ongoing_rx_frame(struct oa_tc6 *tc6, u8 *payload, u32 footer) { … } static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *tc6, u8 *data, u32 footer) { … } static u32 oa_tc6_get_rx_chunk_footer(struct oa_tc6 *tc6, u16 footer_offset) { … } static int oa_tc6_process_spi_data_rx_buf(struct oa_tc6 *tc6, u16 length) { … } static __be32 oa_tc6_prepare_data_header(bool data_valid, bool start_valid, bool end_valid, u8 end_byte_offset) { … } static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6 *tc6) { … } static u16 oa_tc6_prepare_spi_tx_buf_for_tx_skbs(struct oa_tc6 *tc6) { … } static void oa_tc6_add_empty_chunks_to_spi_buf(struct oa_tc6 *tc6, u16 needed_empty_chunks) { … } static u16 oa_tc6_prepare_spi_tx_buf_for_rx_chunks(struct oa_tc6 *tc6, u16 len) { … } static int oa_tc6_try_spi_transfer(struct oa_tc6 *tc6) { … } static int oa_tc6_spi_thread_handler(void *data) { … } static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6) { … } static irqreturn_t oa_tc6_macphy_isr(int irq, void *data) { … } /** * oa_tc6_zero_align_receive_frame_enable - function to enable zero align * receive frame feature. * @tc6: oa_tc6 struct. * * Return: 0 on success otherwise failed. */ int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6) { … } EXPORT_SYMBOL_GPL(…); /** * oa_tc6_start_xmit - function for sending the tx skb which consists ethernet * frame. * @tc6: oa_tc6 struct. * @skb: socket buffer in which the ethernet frame is stored. * * Return: NETDEV_TX_OK if the transmit ethernet frame skb added in the tx_skb_q * otherwise returns NETDEV_TX_BUSY. */ netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb) { … } EXPORT_SYMBOL_GPL(…); /** * oa_tc6_init - allocates and initializes oa_tc6 structure. * @spi: device with which data will be exchanged. * @netdev: network device interface structure. * * Return: pointer reference to the oa_tc6 structure if the MAC-PHY * initialization is successful otherwise NULL. */ struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev) { … } EXPORT_SYMBOL_GPL(…); /** * oa_tc6_exit - exit function. * @tc6: oa_tc6 struct. */ void oa_tc6_exit(struct oa_tc6 *tc6) { … } EXPORT_SYMBOL_GPL(…); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux