linux/drivers/pinctrl/pinctrl-eyeq5.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Pinctrl driver for the Mobileye EyeQ5 platform.
 *
 * The registers are located in a syscon region called OLB. There are two pin
 * banks, each being controlled by 5 registers (see enum eq5p_regs) for
 * pull-down, pull-up, drive strength and muxing.
 *
 * For each pin, muxing is between two functions: (0) GPIO or (1) another one
 * that is pin-dependent. Functions are declared statically in this driver.
 *
 * We create pinctrl groups that are 1:1 equivalent to pins: each group has a
 * single pin, and its index/selector is the pin number.
 *
 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
 *
 * Copyright (C) 2024 Mobileye Vision Technologies Ltd.
 */

#include <linux/array_size.h>
#include <linux/auxiliary_bus.h>
#include <linux/bits.h>
#include <linux/bug.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/types.h>

#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include "core.h"
#include "pinctrl-utils.h"

struct eq5p_pinctrl {};

enum eq5p_bank {};

enum eq5p_regs {};

static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] =;

/*
 * Drive strength; two bits per pin.
 */
#define EQ5P_DS_MASK

/*
 * Comments to the right of each pin are the "signal name" in the datasheet.
 */
static const struct pinctrl_pin_desc eq5p_pins[] =;

static const char * const gpio_groups[] =;

/* Groups of functions on bank A */
static const char * const timer0_groups[] =;
static const char * const timer1_groups[] =;
static const char * const timer2_groups[] =;
static const char * const timer5_groups[] =;
static const char * const uart0_groups[] =;
static const char * const uart1_groups[] =;
static const char * const can0_groups[] =;
static const char * const can1_groups[] =;
static const char * const spi0_groups[] =;
static const char * const spi1_groups[] =;
static const char * const refclk0_groups[] =;

/* Groups of functions on bank B */
static const char * const timer3_groups[] =;
static const char * const timer4_groups[] =;
static const char * const timer6_groups[] =;
static const char * const uart2_groups[] =;
static const char * const can2_groups[] =;
static const char * const spi2_groups[] =;
static const char * const spi3_groups[] =;
static const char * const mclk0_groups[] =;

static const struct pinfunction eq5p_functions[] =;

static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
			     enum eq5p_bank bank, enum eq5p_regs reg,
			     u32 mask, u32 val)
{}

static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,
			  enum eq5p_bank bank, enum eq5p_regs reg, int offset)
{}

static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin)
{}

static unsigned int eq5p_pin_to_offset(unsigned int pin)
{}

static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{}

static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
					       unsigned int selector)
{}

static int eq5p_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
				       unsigned int selector,
				       const unsigned int **pins,
				       unsigned int *num_pins)
{}

static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
			    unsigned long *config)
{}

static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
				      struct seq_file *s,
				      unsigned int pin)
{}

static const struct pinctrl_ops eq5p_pinctrl_ops =;

static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
{}

static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev,
						 unsigned int selector)
{}

static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
					   unsigned int selector,
					   const char * const **groups,
					   unsigned int *num_groups)
{}

static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev,
			       unsigned int func_selector, unsigned int pin)
{}

static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
					   struct pinctrl_gpio_range *range,
					   unsigned int pin)
{}

static const struct pinmux_ops eq5p_pinmux_ops =;

static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev,
					   unsigned int pin, u32 arg)
{}

static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
			    unsigned long *configs, unsigned int num_configs)
{}

static const struct pinconf_ops eq5p_pinconf_ops =;

static int eq5p_probe(struct auxiliary_device *adev,
		      const struct auxiliary_device_id *id)
{}

static const struct auxiliary_device_id eq5p_id_table[] =;
MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table);

static struct auxiliary_driver eq5p_driver =;
module_auxiliary_driver();