/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H /* CAM_CC clocks */ #define CAM_CC_BPS_AHB_CLK … #define CAM_CC_BPS_AREG_CLK … #define CAM_CC_BPS_CLK … #define CAM_CC_BPS_CLK_SRC … #define CAM_CC_CAMNOC_ATB_CLK … #define CAM_CC_CAMNOC_AXI_CLK … #define CAM_CC_CAMNOC_AXI_CLK_SRC … #define CAM_CC_CAMNOC_AXI_HF_CLK … #define CAM_CC_CAMNOC_AXI_SF_CLK … #define CAM_CC_CCI_0_CLK … #define CAM_CC_CCI_0_CLK_SRC … #define CAM_CC_CCI_1_CLK … #define CAM_CC_CCI_1_CLK_SRC … #define CAM_CC_CORE_AHB_CLK … #define CAM_CC_CPAS_AHB_CLK … #define CAM_CC_CPHY_RX_CLK_SRC … #define CAM_CC_CRE_AHB_CLK … #define CAM_CC_CRE_CLK … #define CAM_CC_CRE_CLK_SRC … #define CAM_CC_CSI0PHYTIMER_CLK … #define CAM_CC_CSI0PHYTIMER_CLK_SRC … #define CAM_CC_CSI1PHYTIMER_CLK … #define CAM_CC_CSI1PHYTIMER_CLK_SRC … #define CAM_CC_CSI2PHYTIMER_CLK … #define CAM_CC_CSI2PHYTIMER_CLK_SRC … #define CAM_CC_CSIPHY0_CLK … #define CAM_CC_CSIPHY1_CLK … #define CAM_CC_CSIPHY2_CLK … #define CAM_CC_FAST_AHB_CLK_SRC … #define CAM_CC_ICP_ATB_CLK … #define CAM_CC_ICP_CLK … #define CAM_CC_ICP_CLK_SRC … #define CAM_CC_ICP_CTI_CLK … #define CAM_CC_ICP_TS_CLK … #define CAM_CC_MCLK0_CLK … #define CAM_CC_MCLK0_CLK_SRC … #define CAM_CC_MCLK1_CLK … #define CAM_CC_MCLK1_CLK_SRC … #define CAM_CC_MCLK2_CLK … #define CAM_CC_MCLK2_CLK_SRC … #define CAM_CC_MCLK3_CLK … #define CAM_CC_MCLK3_CLK_SRC … #define CAM_CC_OPE_0_AHB_CLK … #define CAM_CC_OPE_0_AREG_CLK … #define CAM_CC_OPE_0_CLK … #define CAM_CC_OPE_0_CLK_SRC … #define CAM_CC_PLL0 … #define CAM_CC_PLL0_OUT_EVEN … #define CAM_CC_PLL0_OUT_ODD … #define CAM_CC_PLL1 … #define CAM_CC_PLL1_OUT_EVEN … #define CAM_CC_PLL2 … #define CAM_CC_PLL2_OUT_EVEN … #define CAM_CC_PLL3 … #define CAM_CC_PLL3_OUT_EVEN … #define CAM_CC_PLL4 … #define CAM_CC_PLL4_OUT_EVEN … #define CAM_CC_SLOW_AHB_CLK_SRC … #define CAM_CC_SOC_AHB_CLK … #define CAM_CC_SYS_TMR_CLK … #define CAM_CC_TFE_0_AHB_CLK … #define CAM_CC_TFE_0_CLK … #define CAM_CC_TFE_0_CLK_SRC … #define CAM_CC_TFE_0_CPHY_RX_CLK … #define CAM_CC_TFE_0_CSID_CLK … #define CAM_CC_TFE_0_CSID_CLK_SRC … #define CAM_CC_TFE_1_AHB_CLK … #define CAM_CC_TFE_1_CLK … #define CAM_CC_TFE_1_CLK_SRC … #define CAM_CC_TFE_1_CPHY_RX_CLK … #define CAM_CC_TFE_1_CSID_CLK … #define CAM_CC_TFE_1_CSID_CLK_SRC … /* CAM_CC power domains */ #define CAM_CC_CAMSS_TOP_GDSC … /* CAM_CC resets */ #define CAM_CC_BPS_BCR … #define CAM_CC_CAMNOC_BCR … #define CAM_CC_CAMSS_TOP_BCR … #define CAM_CC_CCI_0_BCR … #define CAM_CC_CCI_1_BCR … #define CAM_CC_CPAS_BCR … #define CAM_CC_CRE_BCR … #define CAM_CC_CSI0PHY_BCR … #define CAM_CC_CSI1PHY_BCR … #define CAM_CC_CSI2PHY_BCR … #define CAM_CC_ICP_BCR … #define CAM_CC_MCLK0_BCR … #define CAM_CC_MCLK1_BCR … #define CAM_CC_MCLK2_BCR … #define CAM_CC_MCLK3_BCR … #define CAM_CC_OPE_0_BCR … #define CAM_CC_TFE_0_BCR … #define CAM_CC_TFE_1_BCR … #endif
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