/* SPDX-License-Identifier: GPL-2.0-only */ /* * Analog Devices ADP5585 I/O expander, PWM controller and keypad controller * * Copyright 2022 NXP * Copyright 2024 Ideas on Board Oy */ #ifndef __MFD_ADP5585_H_ #define __MFD_ADP5585_H_ #include <linux/bits.h> #define ADP5585_ID … #define ADP5585_MAN_ID_VALUE … #define ADP5585_MAN_ID_MASK … #define ADP5585_INT_STATUS … #define ADP5585_STATUS … #define ADP5585_FIFO_1 … #define ADP5585_FIFO_2 … #define ADP5585_FIFO_3 … #define ADP5585_FIFO_4 … #define ADP5585_FIFO_5 … #define ADP5585_FIFO_6 … #define ADP5585_FIFO_7 … #define ADP5585_FIFO_8 … #define ADP5585_FIFO_9 … #define ADP5585_FIFO_10 … #define ADP5585_FIFO_11 … #define ADP5585_FIFO_12 … #define ADP5585_FIFO_13 … #define ADP5585_FIFO_14 … #define ADP5585_FIFO_15 … #define ADP5585_FIFO_16 … #define ADP5585_GPI_INT_STAT_A … #define ADP5585_GPI_INT_STAT_B … #define ADP5585_GPI_STATUS_A … #define ADP5585_GPI_STATUS_B … #define ADP5585_RPULL_CONFIG_A … #define ADP5585_RPULL_CONFIG_B … #define ADP5585_RPULL_CONFIG_C … #define ADP5585_RPULL_CONFIG_D … #define ADP5585_Rx_PULL_CFG_PU_300K … #define ADP5585_Rx_PULL_CFG_PD_300K … #define ADP5585_Rx_PULL_CFG_PU_100K … #define ADP5585_Rx_PULL_CFG_DISABLE … #define ADP5585_Rx_PULL_CFG_MASK … #define ADP5585_GPI_INT_LEVEL_A … #define ADP5585_GPI_INT_LEVEL_B … #define ADP5585_GPI_EVENT_EN_A … #define ADP5585_GPI_EVENT_EN_B … #define ADP5585_GPI_INTERRUPT_EN_A … #define ADP5585_GPI_INTERRUPT_EN_B … #define ADP5585_DEBOUNCE_DIS_A … #define ADP5585_DEBOUNCE_DIS_B … #define ADP5585_GPO_DATA_OUT_A … #define ADP5585_GPO_DATA_OUT_B … #define ADP5585_GPO_OUT_MODE_A … #define ADP5585_GPO_OUT_MODE_B … #define ADP5585_GPIO_DIRECTION_A … #define ADP5585_GPIO_DIRECTION_B … #define ADP5585_RESET1_EVENT_A … #define ADP5585_RESET1_EVENT_B … #define ADP5585_RESET1_EVENT_C … #define ADP5585_RESET2_EVENT_A … #define ADP5585_RESET2_EVENT_B … #define ADP5585_RESET_CFG … #define ADP5585_PWM_OFFT_LOW … #define ADP5585_PWM_OFFT_HIGH … #define ADP5585_PWM_ONT_LOW … #define ADP5585_PWM_ONT_HIGH … #define ADP5585_PWM_CFG … #define ADP5585_PWM_IN_AND … #define ADP5585_PWM_MODE … #define ADP5585_PWM_EN … #define ADP5585_LOGIC_CFG … #define ADP5585_LOGIC_FF_CFG … #define ADP5585_LOGIC_INT_EVENT_EN … #define ADP5585_POLL_PTIME_CFG … #define ADP5585_PIN_CONFIG_A … #define ADP5585_PIN_CONFIG_B … #define ADP5585_PIN_CONFIG_C … #define ADP5585_PULL_SELECT … #define ADP5585_C4_EXTEND_CFG_GPIO11 … #define ADP5585_C4_EXTEND_CFG_RESET2 … #define ADP5585_C4_EXTEND_CFG_MASK … #define ADP5585_R4_EXTEND_CFG_GPIO5 … #define ADP5585_R4_EXTEND_CFG_RESET1 … #define ADP5585_R4_EXTEND_CFG_MASK … #define ADP5585_R3_EXTEND_CFG_GPIO4 … #define ADP5585_R3_EXTEND_CFG_LC … #define ADP5585_R3_EXTEND_CFG_PWM_OUT … #define ADP5585_R3_EXTEND_CFG_MASK … #define ADP5585_R0_EXTEND_CFG_GPIO1 … #define ADP5585_R0_EXTEND_CFG_LY … #define ADP5585_R0_EXTEND_CFG_MASK … #define ADP5585_GENERAL_CFG … #define ADP5585_OSC_EN … #define ADP5585_OSC_FREQ_50KHZ … #define ADP5585_OSC_FREQ_100KHZ … #define ADP5585_OSC_FREQ_200KHZ … #define ADP5585_OSC_FREQ_500KHZ … #define ADP5585_OSC_FREQ_MASK … #define ADP5585_INT_CFG … #define ADP5585_RST_CFG … #define ADP5585_INT_EN … #define ADP5585_MAX_REG … /* * Bank 0 covers pins "GPIO 1/R0" to "GPIO 6/R5", numbered 0 to 5 by the * driver, and bank 1 covers pins "GPIO 7/C0" to "GPIO 11/C4", numbered 6 to * 10. Some variants of the ADP5585 don't support "GPIO 6/R5". As the driver * uses identical GPIO numbering for all variants to avoid confusion, GPIO 5 is * marked as reserved in the device tree for variants that don't support it. */ #define ADP5585_BANK(n) … #define ADP5585_BIT(n) … struct regmap; struct adp5585_dev { … }; #endif
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