/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_ENGINE_REGS__ #define __INTEL_ENGINE_REGS__ #include "i915_reg_defs.h" #define RING_EXCC(base) … #define RING_TAIL(base) … #define TAIL_ADDR … #define RING_HEAD(base) … #define HEAD_WRAP_COUNT … #define HEAD_WRAP_ONE … #define HEAD_ADDR … #define RING_START(base) … #define RING_CTL(base) … #define RING_CTL_SIZE(size) … #define RING_NR_PAGES … #define RING_REPORT_MASK … #define RING_REPORT_64K … #define RING_REPORT_128K … #define RING_NO_REPORT … #define RING_VALID_MASK … #define RING_VALID … #define RING_INVALID … #define RING_WAIT_I8XX … #define RING_WAIT … #define RING_WAIT_SEMAPHORE … #define RING_SYNC_0(base) … #define RING_SYNC_1(base) … #define RING_SYNC_2(base) … #define GEN6_RVSYNC … #define GEN6_RBSYNC … #define GEN6_RVESYNC … #define GEN6_VBSYNC … #define GEN6_VRSYNC … #define GEN6_VVESYNC … #define GEN6_BRSYNC … #define GEN6_BVSYNC … #define GEN6_BVESYNC … #define GEN6_VEBSYNC … #define GEN6_VERSYNC … #define GEN6_VEVSYNC … #define RING_PSMI_CTL(base) … #define GEN8_RC_SEMA_IDLE_MSG_DISABLE … #define GEN8_FF_DOP_CLOCK_GATE_DISABLE … #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE … #define GEN6_BSD_GO_INDICATOR … #define GEN6_BSD_SLEEP_INDICATOR … #define GEN6_BSD_SLEEP_FLUSH_DISABLE … #define GEN6_PSMI_SLEEP_MSG_DISABLE … #define RING_MAX_IDLE(base) … #define PWRCTX_MAXCNT(base) … #define IDLE_TIME_MASK … #define RING_ACTHD_UDW(base) … #define RING_DMA_FADD_UDW(base) … #define RING_IPEIR(base) … #define RING_IPEHR(base) … #define RING_INSTDONE(base) … #define RING_INSTPS(base) … #define RING_DMA_FADD(base) … #define RING_ACTHD(base) … #define RING_HWS_PGA(base) … #define RING_CMD_BUF_CCTL(base) … #define IPEIR(base) … #define IPEHR(base) … #define RING_ID(base) … #define RING_NOPID(base) … #define RING_HWSTAM(base) … #define RING_MI_MODE(base) … #define ASYNC_FLIP_PERF_DISABLE … #define MI_FLUSH_ENABLE … #define TGL_NESTED_BB_EN … #define MODE_IDLE … #define STOP_RING … #define VS_TIMER_DISPATCH … #define RING_IMR(base) … #define RING_EIR(base) … #define RING_EMR(base) … #define RING_ESR(base) … #define GEN12_STATE_ACK_DEBUG(base) … #define RING_INSTPM(base) … #define RING_CMD_CCTL(base) … #define ACTHD(base) … #define GEN8_R_PWR_CLK_STATE(base) … #define GEN8_RPCS_ENABLE … #define GEN8_RPCS_S_CNT_ENABLE … #define GEN8_RPCS_S_CNT_SHIFT … #define GEN8_RPCS_S_CNT_MASK … #define GEN11_RPCS_S_CNT_SHIFT … #define GEN11_RPCS_S_CNT_MASK … #define GEN8_RPCS_SS_CNT_ENABLE … #define GEN8_RPCS_SS_CNT_SHIFT … #define GEN8_RPCS_SS_CNT_MASK … #define GEN8_RPCS_EU_MAX_SHIFT … #define GEN8_RPCS_EU_MAX_MASK … #define GEN8_RPCS_EU_MIN_SHIFT … #define GEN8_RPCS_EU_MIN_MASK … #define RING_RESET_CTL(base) … #define RESET_CTL_CAT_ERROR … #define RESET_CTL_READY_TO_RESET … #define RESET_CTL_REQUEST_RESET … #define DMA_FADD_I8XX(base) … #define RING_BBSTATE(base) … #define RING_BB_PPGTT … #define RING_SBBADDR(base) … #define RING_SBBSTATE(base) … #define RING_SBBADDR_UDW(base) … #define RING_BBADDR(base) … #define RING_BB_OFFSET(base) … #define RING_BBADDR_UDW(base) … #define CCID(base) … #define CCID_EN … #define CCID_EXTENDED_STATE_RESTORE … #define CCID_EXTENDED_STATE_SAVE … #define RING_BB_PER_CTX_PTR(base) … #define PER_CTX_BB_FORCE … #define PER_CTX_BB_VALID … #define RING_INDIRECT_CTX(base) … #define RING_INDIRECT_CTX_OFFSET(base) … #define ECOSKPD(base) … #define XEHP_BLITTER_SCHEDULING_MODE_MASK … #define XEHP_BLITTER_ROUND_ROBIN_MODE … #define ECO_CONSTANT_BUFFER_SR_DISABLE … #define ECO_GATING_CX_ONLY … #define GEN6_BLITTER_FBC_NOTIFY … #define ECO_FLIP_DONE … #define GEN6_BLITTER_LOCK_SHIFT … #define BLIT_CCTL(base) … #define BLIT_CCTL_DST_MOCS_MASK … #define BLIT_CCTL_SRC_MOCS_MASK … #define BLIT_CCTL_MASK … #define BLIT_CCTL_MOCS(dst, src) … #define RING_CSCMDOP(base) … /* * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. * The lsb of each can be considered a separate enabling bit for encryption. * 6:0 == default MOCS value for reads => 6:1 == table index for reads. * 13:7 == default MOCS value for writes => 13:8 == table index for writes. * 15:14 == Reserved => 31:30 are set to 0. */ #define CMD_CCTL_WRITE_OVERRIDE_MASK … #define CMD_CCTL_READ_OVERRIDE_MASK … #define CMD_CCTL_MOCS_MASK … #define CMD_CCTL_MOCS_OVERRIDE(write, read) … #define RING_PREDICATE_RESULT(base) … #define MI_PREDICATE_RESULT_2(base) … #define LOWER_SLICE_ENABLED … #define LOWER_SLICE_DISABLED … #define MI_PREDICATE_SRC0(base) … #define MI_PREDICATE_SRC0_UDW(base) … #define MI_PREDICATE_SRC1(base) … #define MI_PREDICATE_SRC1_UDW(base) … #define MI_PREDICATE_DATA(base) … #define MI_PREDICATE_RESULT(base) … #define MI_PREDICATE_RESULT_1(base) … #define RING_PP_DIR_DCLV(base) … #define PP_DIR_DCLV_2G … #define RING_PP_DIR_BASE(base) … #define RING_ELSP(base) … #define RING_EXECLIST_STATUS_LO(base) … #define RING_EXECLIST_STATUS_HI(base) … #define RING_CONTEXT_CONTROL(base) … #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT … #define CTX_CTRL_RS_CTX_ENABLE … #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT … #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH … #define GEN12_CTX_CTRL_RUNALONE_MODE … #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE … #define RING_CTX_SR_CTL(base) … #define RING_SEMA_WAIT_POLL(base) … #define GEN8_RING_PDP_UDW(base, n) … #define GEN8_RING_PDP_LDW(base, n) … #define RING_MODE_GEN7(base) … #define GFX_RUN_LIST_ENABLE … #define GFX_INTERRUPT_STEERING … #define GFX_TLB_INVALIDATE_EXPLICIT … #define GFX_SURFACE_FAULT_ENABLE … #define GFX_REPLAY_MODE … #define GFX_PSMI_GRANULARITY … #define GEN12_GFX_PREFETCH_DISABLE … #define GFX_PPGTT_ENABLE … #define GEN8_GFX_PPGTT_48B … #define GFX_FORWARD_VBLANK_MASK … #define GFX_FORWARD_VBLANK_NEVER … #define GFX_FORWARD_VBLANK_ALWAYS … #define GFX_FORWARD_VBLANK_COND … #define GEN11_GFX_DISABLE_LEGACY_MODE … #define RING_TIMESTAMP(base) … #define RING_TIMESTAMP_UDW(base) … #define RING_CONTEXT_STATUS_PTR(base) … #define RING_CTX_TIMESTAMP(base) … #define RING_PREDICATE_RESULT(base) … #define MI_PREDICATE_RESULT_2_ENGINE(base) … #define RING_FORCE_TO_NONPRIV(base, i) … #define RING_FORCE_TO_NONPRIV_DENY … #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK … #define RING_FORCE_TO_NONPRIV_ACCESS_RW … #define RING_FORCE_TO_NONPRIV_ACCESS_RD … #define RING_FORCE_TO_NONPRIV_ACCESS_WR … #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID … #define RING_FORCE_TO_NONPRIV_ACCESS_MASK … #define RING_FORCE_TO_NONPRIV_RANGE_1 … #define RING_FORCE_TO_NONPRIV_RANGE_4 … #define RING_FORCE_TO_NONPRIV_RANGE_16 … #define RING_FORCE_TO_NONPRIV_RANGE_64 … #define RING_FORCE_TO_NONPRIV_RANGE_MASK … #define RING_FORCE_TO_NONPRIV_MASK_VALID … #define RING_MAX_NONPRIV_SLOTS … #define RING_EXECLIST_SQ_CONTENTS(base) … #define RING_PP_DIR_BASE_READ(base) … #define RING_EXECLIST_CONTROL(base) … #define EL_CTRL_LOAD … /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ #define GEN8_RING_CS_GPR(base, n) … #define GEN8_RING_CS_GPR_UDW(base, n) … #define GEN11_VCS_SFC_FORCED_LOCK(base) … #define GEN11_VCS_SFC_FORCED_LOCK_BIT … #define GEN11_VCS_SFC_LOCK_STATUS(base) … #define GEN11_VCS_SFC_USAGE_BIT … #define GEN11_VCS_SFC_LOCK_ACK_BIT … #define GEN11_VECS_SFC_FORCED_LOCK(base) … #define GEN11_VECS_SFC_FORCED_LOCK_BIT … #define GEN11_VECS_SFC_LOCK_ACK(base) … #define GEN11_VECS_SFC_LOCK_ACK_BIT … #define GEN11_VECS_SFC_USAGE(base) … #define GEN11_VECS_SFC_USAGE_BIT … #define RING_HWS_PGA_GEN6(base) … #define GEN12_HCP_SFC_LOCK_STATUS(base) … #define GEN12_HCP_SFC_LOCK_ACK_BIT … #define GEN12_HCP_SFC_USAGE_BIT … #define VDBOX_CGCTL3F10(base) … #define IECPUNIT_CLKGATE_DIS … #define VDBOX_CGCTL3F18(base) … #define ALNUNIT_CLKGATE_DIS … #define VDBOX_CGCTL3F1C(base) … #define MFXPIPE_CLKGATE_DIS … #endif /* __INTEL_ENGINE_REGS__ */
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