linux/drivers/gpu/drm/i915/gt/intel_sseu.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2019 Intel Corporation
 */

#ifndef __INTEL_SSEU_H__
#define __INTEL_SSEU_H__

#include <linux/types.h>
#include <linux/kernel.h>

#include "i915_gem.h"

struct drm_i915_private;
struct intel_gt;
struct drm_printer;

/*
 * Maximum number of slices on older platforms.  Slices no longer exist
 * starting on Xe_HP ("gslices," "cslices," etc. are a different concept and
 * are not expressed through fusing).
 */
#define GEN_MAX_HSW_SLICES …

/*
 * Maximum number of subslices that can exist within a HSW-style slice.  This
 * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
 * I915_MAX_SS_FUSE_BITS value below).
 */
#define GEN_MAX_SS_PER_HSW_SLICE …

/*
 * Maximum number of 32-bit registers used by hardware to express the
 * enabled/disabled subslices.
 */
#define I915_MAX_SS_FUSE_REGS …
#define I915_MAX_SS_FUSE_BITS …

/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS …

#define SSEU_MAX(a, b) …

/* The maximum number of bits needed to express each subslice/DSS independently */
#define GEN_SS_MASK_SIZE …

#define GEN_SSEU_STRIDE(max_entries) …
#define GEN_MAX_SUBSLICE_STRIDE …
#define GEN_MAX_EU_STRIDE …

#define GEN_DSS_PER_GSLICE …
#define GEN_DSS_PER_CSLICE …
#define GEN_DSS_PER_MSLICE …

#define GEN_MAX_GSLICES …
#define GEN_MAX_CSLICES …

intel_sseu_ss_mask_t;

#define XEHP_BITMAP_BITS(mask) …

struct sseu_dev_info { … };

/*
 * Powergating configuration for a particular (context,engine).
 */
struct intel_sseu { … };

static inline struct intel_sseu
intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{ … }

static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
			int subslice)
{ … }

/*
 * Used to obtain the index of the first DSS.  Can start searching from the
 * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
 * groupsize and groupnum are non-zero.
 */
static inline unsigned int
intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
			       int groupnum)
{ … }

void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
			 u8 max_subslices, u8 max_eus_per_subslice);

unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);

unsigned int
intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);

intel_sseu_ss_mask_t
intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);

void intel_sseu_info_init(struct intel_gt *gt);

u32 intel_sseu_make_rpcs(struct intel_gt *gt,
			 const struct intel_sseu *req_sseu);

void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
void intel_sseu_print_topology(struct drm_i915_private *i915,
			       const struct sseu_dev_info *sseu,
			       struct drm_printer *p);

u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);

int intel_sseu_copy_eumask_to_user(void __user *to,
				   const struct sseu_dev_info *sseu);
int intel_sseu_copy_ssmask_to_user(void __user *to,
				   const struct sseu_dev_info *sseu);

void intel_sseu_print_ss_info(const char *type,
			      const struct sseu_dev_info *sseu,
			      struct seq_file *m);

#endif /* __INTEL_SSEU_H__ */