/* * Copyright © 2017 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * */ #ifndef __INTEL_UNCORE_H__ #define __INTEL_UNCORE_H__ #include <linux/spinlock.h> #include <linux/notifier.h> #include <linux/hrtimer.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/types.h> #include "i915_reg_defs.h" struct drm_device; struct drm_i915_private; struct intel_runtime_pm; struct intel_uncore; struct intel_gt; struct intel_uncore_mmio_debug { … }; enum forcewake_domain_id { … }; enum forcewake_domains { … }; struct intel_uncore_fw_get { … }; struct intel_uncore_funcs { … }; struct intel_forcewake_range { … }; /* Other register ranges (e.g., shadow tables, MCR tables, etc.) */ struct i915_range { … }; struct intel_uncore { … }; /* Iterate over initialised fw domains */ #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) … #define for_each_fw_domain(domain__, uncore__, tmp__) … static inline bool intel_uncore_has_forcewake(const struct intel_uncore *uncore) { … } static inline bool intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore) { … } static inline bool intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore) { … } static inline bool intel_uncore_has_fifo(const struct intel_uncore *uncore) { … } static inline bool intel_uncore_needs_flr_on_fini(const struct intel_uncore *uncore) { … } static inline bool intel_uncore_set_flr_on_fini(struct intel_uncore *uncore) { … } void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915); void intel_uncore_init_early(struct intel_uncore *uncore, struct intel_gt *gt); int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr); int intel_uncore_init_mmio(struct intel_uncore *uncore); void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, struct intel_gt *gt); bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); void intel_uncore_cleanup_mmio(struct intel_uncore *uncore); void intel_uncore_fini_mmio(struct drm_device *dev, void *data); void intel_uncore_suspend(struct intel_uncore *uncore); void intel_uncore_resume_early(struct intel_uncore *uncore); void intel_uncore_runtime_resume(struct intel_uncore *uncore); void assert_forcewakes_inactive(struct intel_uncore *uncore); void assert_forcewakes_active(struct intel_uncore *uncore, enum forcewake_domains fw_domains); const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); enum forcewake_domains intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, i915_reg_t reg, unsigned int op); #define FW_REG_READ … #define FW_REG_WRITE … void intel_uncore_forcewake_get(struct intel_uncore *uncore, enum forcewake_domains domains); void intel_uncore_forcewake_put(struct intel_uncore *uncore, enum forcewake_domains domains); void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, enum forcewake_domains domains); void intel_uncore_forcewake_flush(struct intel_uncore *uncore, enum forcewake_domains fw_domains); /* * Like above but the caller must manage the uncore.lock itself. * Must be used with intel_uncore_read_fw() and friends. */ void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, enum forcewake_domains domains); void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, enum forcewake_domains domains); void intel_uncore_forcewake_user_get(struct intel_uncore *uncore); void intel_uncore_forcewake_user_put(struct intel_uncore *uncore); int __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value); static inline int intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms) { … } int __intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value); static inline int intel_wait_for_register_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms) { … } #define IS_GSI_REG(reg) … /* register access functions */ #define __raw_read … #define __raw_write … __raw_read __raw_read __raw_read __raw_read __raw_write __raw_write __raw_write __raw_write #undef __raw_read #undef __raw_write #define __uncore_read … #define __uncore_write … __uncore_read __uncore_read __uncore_read __uncore_read __uncore_read __uncore_write __uncore_write __uncore_write __uncore_write /* Be very careful with read/write 64-bit values. On 32-bit machines, they * will be implemented using 2 32-bit writes in an arbitrary order with * an arbitrary delay between them. This can cause the hardware to * act upon the intermediate value, possibly leading to corruption and * machine death. For this reason we do not support intel_uncore_write64, * or uncore->funcs.mmio_writeq. * * When reading a 64-bit value as two 32-bit values, the delay may cause * the two reads to mismatch, e.g. a timestamp overflowing. Also note that * occasionally a 64-bit register does not actually support a full readq * and must be read using two 32-bit reads. * * You have been warned. */ __uncore_read #define intel_uncore_posting_read(...) … #define intel_uncore_posting_read16(...) … #undef __uncore_read #undef __uncore_write /* These are untraced mmio-accessors that are only valid to be used inside * critical sections, such as inside IRQ handlers, where forcewake is explicitly * controlled. * * Think twice, and think again, before using these. * * As an example, these accessors can possibly be used between: * * spin_lock_irq(&uncore->lock); * intel_uncore_forcewake_get__locked(); * * and * * intel_uncore_forcewake_put__locked(); * spin_unlock_irq(&uncore->lock); * * * Note: some registers may not need forcewake held, so * intel_uncore_forcewake_{get,put} can be omitted, see * intel_uncore_forcewake_for_reg(). * * Certain architectures will die if the same cacheline is concurrently accessed * by different clients (e.g. on Ivybridge). Access to registers should * therefore generally be serialised, by either the dev_priv->uncore.lock or * a more localised lock guarding all access to that bank of registers. */ #define intel_uncore_read_fw(...) … #define intel_uncore_write_fw(...) … #define intel_uncore_write64_fw(...) … #define intel_uncore_posting_read_fw(...) … static inline u32 intel_uncore_rmw(struct intel_uncore *uncore, i915_reg_t reg, u32 clear, u32 set) { … } static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clear, u32 set) { … } static inline u64 intel_uncore_read64_2x32(struct intel_uncore *uncore, i915_reg_t lower_reg, i915_reg_t upper_reg) { … } static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore, i915_reg_t reg, u32 val, u32 mask, u32 expected_val) { … } static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore) { … } /* * The raw_reg_{read,write} macros are intended as a micro-optimization for * interrupt handlers so that the pointer indirection on uncore->regs can * be computed once (and presumably cached in a register) instead of generating * extra load instructions for each MMIO access. * * Given that these macros are only intended for non-GSI interrupt registers * (and the goal is to avoid extra instructions generated by the compiler), * these macros do not account for uncore->gsi_offset. Any caller that needs * to use these macros on a GSI register is responsible for adding the * appropriate GSI offset to the 'base' parameter. */ #define raw_reg_read(base, reg) … #define raw_reg_write(base, reg, value) … #endif /* !__INTEL_UNCORE_H__ */
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