/* SPDX-License-Identifier: MIT */ /* * Copyright © 2019 Intel Corporation */ #ifndef __INTEL_ENGINE_TYPES__ #define __INTEL_ENGINE_TYPES__ #include <linux/average.h> #include <linux/hashtable.h> #include <linux/irq_work.h> #include <linux/kref.h> #include <linux/list.h> #include <linux/llist.h> #include <linux/rbtree.h> #include <linux/timer.h> #include <linux/types.h> #include <linux/workqueue.h> #include "i915_gem.h" #include "i915_pmu.h" #include "i915_priolist_types.h" #include "i915_selftest.h" #include "intel_sseu.h" #include "intel_timeline_types.h" #include "intel_uncore.h" #include "intel_wakeref.h" #include "intel_workarounds_types.h" /* HW Engine class + instance */ #define RENDER_CLASS … #define VIDEO_DECODE_CLASS … #define VIDEO_ENHANCEMENT_CLASS … #define COPY_ENGINE_CLASS … #define OTHER_CLASS … #define COMPUTE_CLASS … #define MAX_ENGINE_CLASS … #define MAX_ENGINE_INSTANCE … #define I915_MAX_SLICES … #define I915_MAX_SUBSLICES … #define I915_CMD_HASH_ORDER … struct dma_fence; struct drm_i915_gem_object; struct drm_i915_reg_table; struct i915_gem_context; struct i915_request; struct i915_sched_attr; struct i915_sched_engine; struct intel_gt; struct intel_ring; struct intel_uncore; struct intel_breadcrumbs; struct intel_engine_cs; struct i915_perf_group; intel_engine_mask_t; #define ALL_ENGINES … #define VIRTUAL_ENGINES … struct intel_hw_status_page { … }; struct intel_instdone { … }; /* * we use a single page to load ctx workarounds so all of these * values are referred in terms of dwords * * struct i915_wa_ctx_bb: * offset: specifies batch starting position, also helpful in case * if we want to have multiple batches at different offsets based on * some criteria. It is not a requirement at the moment but provides * an option for future use. * size: size of the batch in DWORDS */ struct i915_ctx_workarounds { … }; #define I915_MAX_VCS … #define I915_MAX_VECS … #define I915_MAX_SFC … #define I915_MAX_CCS … #define I915_MAX_RCS … #define I915_MAX_BCS … /* * Engine IDs definitions. * Keep instances of the same type engine together. */ enum intel_engine_id { … }; /* A simple estimator for the round-trip latency of an engine */ DECLARE_EWMA(_engine_latency, 6, 4) struct st_preempt_hang { … }; /** * struct intel_engine_execlists - execlist submission queue and port state * * The struct intel_engine_execlists represents the combined logical state of * driver and the hardware state for execlist mode of submission. */ struct intel_engine_execlists { … }; #define INTEL_ENGINE_CS_MAX_NAME … struct intel_engine_execlists_stats { … }; struct intel_engine_guc_stats { … }; intel_engine_tlb_inv_reg; struct intel_engine_tlb_inv { … }; struct intel_engine_cs { … }; static inline bool intel_engine_using_cmd_parser(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_supports_stats(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_has_preemption(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_has_semaphores(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_has_timeslices(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_is_virtual(const struct intel_engine_cs *engine) { … } static inline bool intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine) { … } /* Wa_14014475959:dg2 */ /* Wa_16019325821 */ /* Wa_14019159160 */ static inline bool intel_engine_uses_wa_hold_switchout(struct intel_engine_cs *engine) { … } #endif /* __INTEL_ENGINE_TYPES_H__ */
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