/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_GT_REGS__ #define __INTEL_GT_REGS__ #include "i915_reg_defs.h" #define VLV_GUNIT_BASE … /* * The perf control registers are technically multicast registers, but the * driver never needs to read/write them directly; we only use them to build * lists of registers (where they're mixed in with other non-MCR registers) * and then operate on the offset directly. For now we'll just define them * as non-multicast so we can place them on the same list, but we may want * to try to come up with a better way to handle heterogeneous lists of * registers in the future. */ #define PERF_REG(offset) … /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ #define MTL_MIRROR_TARGET_WP1 … #define MTL_CAGF_MASK … #define MTL_CC0 … #define MTL_CC6 … #define MTL_CC_MASK … /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 … #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT … #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK … #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ … #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ … #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT … #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK … #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ … #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ … #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ … #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ … #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT … #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK … #define RPM_CONFIG1 … #define GEN10_GT_NOA_ENABLE … /* RCP unit config (Gen8+) */ #define RCP_CONFIG … #define RC6_LOCATION … #define RC6_CTX_IN_DRAM … #define RC6_CTX_BASE … #define RC6_CTX_BASE_MASK … #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) … #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) … #define FORCEWAKE_ACK_RENDER_GEN9 … #define FORCEWAKE_ACK_MEDIA_GEN9 … #define FORCEWAKE_ACK_GSC … #define FORCEWAKE_ACK_GT_MTL … #define GMD_ID_GRAPHICS … #define GMD_ID_MEDIA … #define MCFG_MCR_SELECTOR … #define MTL_STEER_SEMAPHORE … #define MTL_MCR_SELECTOR … #define SF_MCR_SELECTOR … #define GEN8_MCR_SELECTOR … #define GAM_MCR_SELECTOR … #define GEN8_MCR_SLICE(slice) … #define GEN8_MCR_SLICE_MASK … #define GEN8_MCR_SUBSLICE(subslice) … #define GEN8_MCR_SUBSLICE_MASK … #define GEN11_MCR_MULTICAST … #define GEN11_MCR_SLICE(slice) … #define GEN11_MCR_SLICE_MASK … #define GEN11_MCR_SUBSLICE(subslice) … #define GEN11_MCR_SUBSLICE_MASK … #define MTL_MCR_GROUPID … #define MTL_MCR_INSTANCEID … #define IPEIR_I965 … #define IPEHR_I965 … /* * On GEN4, only the render ring INSTDONE exists and has a different * layout than the GEN7+ version. * The GEN2 counterpart of this register is GEN2_INSTDONE. */ #define INSTPS … #define GEN4_INSTDONE1 … #define ACTHD_I965 … #define HWS_PGA … #define HWS_ADDRESS_MASK … #define HWS_START_ADDRESS_SHIFT … #define _3D_CHICKEN … #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB … #define PWRCTXA … #define PWRCTX_EN … #define FF_SLICE_CHICKEN … #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX … /* GM45+ chicken bits -- debug workaround bits that may be required * for various sorts of correct behavior. The top 16 bits of each are * the enables for writing to the corresponding low bit. */ #define _3D_CHICKEN2 … /* Disables pipelining of read flushes past the SF-WIZ interface. * Required on all Ironlake steppings according to the B-Spec, but the * particular danger of not doing so is not specified. */ #define _3D_CHICKEN2_WM_READ_PIPELINED … #define _3D_CHICKEN3 … #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX … #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL … #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE … #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL … #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) … #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH … #define GEN2_INSTDONE … #define NOPID … #define HWSTAM … #define WAIT_FOR_RC6_EXIT … /* HSW only */ #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT … #define HSW_SELECTIVE_READ_ADDRESSING_MASK … #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT … #define HSW_SELECTIVE_WRITE_ADDRESS_MASK … /* HSW+ */ #define HSW_WAIT_FOR_RC6_EXIT_ENABLE … #define HSW_RCS_CONTEXT_ENABLE … #define HSW_RCS_INHIBIT … /* Gen8 */ #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT … #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK … #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT … #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK … #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE … #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT … #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK … #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT … #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK … #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE … #define GEN6_GT_MODE … #define GEN6_WIZ_HASHING(hi, lo) … #define GEN6_WIZ_HASHING_8x8 … #define GEN6_WIZ_HASHING_8x4 … #define GEN6_WIZ_HASHING_16x4 … #define GEN6_WIZ_HASHING_MASK … #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE … /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ #define GEN9_CSFE_CHICKEN1_RCS … #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE … #define GEN11_ENABLE_32_PLANE_MODE … #define GEN12_CS_DEBUG_MODE2 … #define INSTRUCTION_STATE_CACHE_INVALIDATE … #define GEN7_FF_SLICE_CS_CHICKEN1 … #define GEN9_FFSC_PERCTX_PREEMPT_CTRL … #define FF_SLICE_CS_CHICKEN2 … #define GEN9_TSG_BARRIER_ACK_DISABLE … #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE … #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE … #define GEN9_CS_DEBUG_MODE1 … #define FF_DOP_CLOCK_GATE_DISABLE … #define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON … #define GEN12_REPLAY_MODE_GRANULARITY … /* WaClearTdlStateAckDirtyBits */ #define GEN8_STATE_ACK … #define GEN9_STATE_ACK_SLICE1 … #define GEN9_STATE_ACK_SLICE2 … #define GEN9_STATE_ACK_TDL0 … #define GEN9_STATE_ACK_TDL1 … #define GEN9_STATE_ACK_TDL2 … #define GEN9_STATE_ACK_TDL3 … #define GEN9_SUBSLICE_TDL_ACK_BITS … #define CACHE_MODE_0 … #define CM0_PIPELINED_RENDER_FLUSH_DISABLE … #define CM0_IZ_OPT_DISABLE … #define CM0_ZR_OPT_DISABLE … #define CM0_STC_EVICT_DISABLE_LRA_SNB … #define CM0_DEPTH_EVICT_DISABLE … #define CM0_COLOR_EVICT_DISABLE … #define CM0_DEPTH_WRITE_DISABLE … #define CM0_RC_OP_FLUSH_DISABLE … #define GFX_FLSH_CNTL … /* * Logical Context regs */ /* * Notes on SNB/IVB/VLV context size: * - Power context is saved elsewhere (LLC or stolen) * - Ring/execlist context is saved on SNB, not on IVB * - Extended context size already includes render context size * - We always need to follow the extended context size. * SNB BSpec has comments indicating that we should use the * render context size instead if execlists are disabled, but * based on empirical testing that's just nonsense. * - Pipelined/VF state is saved on SNB/IVB respectively * - GT1 size just indicates how much of render context * doesn't need saving on GT1 */ #define CXT_SIZE … #define GEN6_CXT_POWER_SIZE(cxt_reg) … #define GEN6_CXT_RING_SIZE(cxt_reg) … #define GEN6_CXT_RENDER_SIZE(cxt_reg) … #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) … #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) … #define GEN6_CXT_TOTAL_SIZE(cxt_reg) … #define GEN7_CXT_SIZE … #define GEN7_CXT_POWER_SIZE(ctx_reg) … #define GEN7_CXT_RING_SIZE(ctx_reg) … #define GEN7_CXT_RENDER_SIZE(ctx_reg) … #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) … #define GEN7_CXT_GT1_SIZE(ctx_reg) … #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) … #define GEN7_CXT_TOTAL_SIZE(ctx_reg) … #define HSW_MI_PREDICATE_RESULT_2 … #define GEN9_CTX_PREEMPT_REG … #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG … #define GPGPU_THREADS_DISPATCHED … #define GPGPU_THREADS_DISPATCHED_UDW … #define GEN9_RCS_FE_FSM2 … #define GEN6_RCS_PWR_FSM … #define HS_INVOCATION_COUNT … #define HS_INVOCATION_COUNT_UDW … #define DS_INVOCATION_COUNT … #define DS_INVOCATION_COUNT_UDW … #define IA_VERTICES_COUNT … #define IA_VERTICES_COUNT_UDW … #define IA_PRIMITIVES_COUNT … #define IA_PRIMITIVES_COUNT_UDW … #define VS_INVOCATION_COUNT … #define VS_INVOCATION_COUNT_UDW … #define GS_INVOCATION_COUNT … #define GS_INVOCATION_COUNT_UDW … #define GS_PRIMITIVES_COUNT … #define GS_PRIMITIVES_COUNT_UDW … #define CL_INVOCATION_COUNT … #define CL_INVOCATION_COUNT_UDW … #define CL_PRIMITIVES_COUNT … #define CL_PRIMITIVES_COUNT_UDW … #define PS_INVOCATION_COUNT … #define PS_INVOCATION_COUNT_UDW … #define PS_DEPTH_COUNT … #define PS_DEPTH_COUNT_UDW … #define GEN7_3DPRIM_END_OFFSET … #define GEN7_3DPRIM_START_VERTEX … #define GEN7_3DPRIM_VERTEX_COUNT … #define GEN7_3DPRIM_INSTANCE_COUNT … #define GEN7_3DPRIM_START_INSTANCE … #define GEN7_3DPRIM_BASE_VERTEX … #define GEN7_GPGPU_DISPATCHDIMX … #define GEN7_GPGPU_DISPATCHDIMY … #define GEN7_GPGPU_DISPATCHDIMZ … #define GFX_MODE … #define GEN8_CS_CHICKEN1 … #define GEN9_PREEMPT_3D_OBJECT_LEVEL … #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) … #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL … #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL … #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL … #define GEN9_PREEMPT_GPGPU_LEVEL_MASK … #define DRAW_WATERMARK … #define VERT_WM_VAL … #define GEN12_GLOBAL_MOCS(i) … #define RENDER_HWS_PGA_GEN7 … #define GEN8_GAMW_ECO_DEV_RW_IA … #define GAMW_ECO_ENABLE_64K_IPS_FIELD … #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE … #define GAM_ECOCHK … #define BDW_DISABLE_HDC_INVALIDATION … #define ECOCHK_SNB_BIT … #define ECOCHK_DIS_TLB … #define HSW_ECOCHK_ARB_PRIO_SOL … #define ECOCHK_PPGTT_CACHE64B … #define ECOCHK_PPGTT_CACHE4B … #define ECOCHK_PPGTT_GFDT_IVB … #define ECOCHK_PPGTT_LLC_IVB … #define ECOCHK_PPGTT_UC_HSW … #define ECOCHK_PPGTT_WT_HSW … #define ECOCHK_PPGTT_WB_HSW … #define GEN8_RING_FAULT_REG … #define _RING_FAULT_REG_RCS … #define _RING_FAULT_REG_VCS … #define _RING_FAULT_REG_BCS … #define _RING_FAULT_REG_VECS … #define RING_FAULT_REG(engine) … #define ERROR_GEN6 … #define DONE_REG … #define GEN8_PRIVATE_PAT_LO … #define GEN8_PRIVATE_PAT_HI … #define GEN10_PAT_INDEX(index) … #define BSD_HWS_PGA_GEN7 … #define GEN12_CCS_AUX_INV … #define GEN12_VD0_AUX_INV … #define GEN12_VE0_AUX_INV … #define GEN12_BCS0_AUX_INV … #define GEN8_RTCR … #define GEN8_M1TCR … #define GEN8_M2TCR … #define GEN8_BTCR … #define GEN8_VTCR … #define BLT_HWS_PGA_GEN7 … #define GEN12_VD2_AUX_INV … #define GEN12_CCS0_AUX_INV … #define AUX_INV … #define VEBOX_HWS_PGA_GEN7 … #define GEN12_AUX_ERR_DBG … #define GEN7_TLB_RD_ADDR … #define GEN12_PAT_INDEX(index) … #define _PAT_INDEX(index) … #define XEHP_PAT_INDEX(index) … #define XELPMP_PAT_INDEX(index) … #define XEHP_TILE0_ADDR_RANGE … #define XEHP_TILE_LMEM_RANGE_SHIFT … #define XEHP_FLAT_CCS_BASE_ADDR … #define XEHP_CCS_BASE_SHIFT … #define GAMTARBMODE … #define ARB_MODE_BWGTLB_DISABLE … #define ARB_MODE_SWIZZLE_BDW … #define GEN9_GAMT_ECO_REG_RW_IA … #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS … #define GAMT_CHKN_BIT_REG … #define GAMT_CHKN_DISABLE_L3_COH_PIPE … #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING … #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT … #define GEN8_FAULT_TLB_DATA0 … #define GEN8_FAULT_TLB_DATA1 … #define GEN11_GACB_PERF_CTRL … #define GEN11_HASH_CTRL_MASK … #define GEN11_HASH_CTRL_BIT0 … #define GEN11_HASH_CTRL_BIT4 … /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU … #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW … #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV … #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL … #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT … #define MMCD_MISC_CTRL … #define MMCD_PCLA … #define MMCD_HOTSPOT_EN … /* There are the 4 64-bit counter registers, one for each stream output */ #define GEN7_SO_NUM_PRIMS_WRITTEN(n) … #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) … #define GEN7_SO_PRIM_STORAGE_NEEDED(n) … #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) … #define GEN9_WM_CHICKEN3 … #define GEN9_FACTOR_IN_CLR_VAL_HIZ … #define XEHP_CULLBIT1 … #define CHICKEN_RASTER_2 … #define TBIMR_FAST_CLIP … #define VFLSKPD … #define VF_PREFETCH_TLB_DIS … #define DIS_OVER_FETCH_CACHE … #define DIS_MULT_MISS_RD_SQUASH … #define GEN12_FF_MODE2 … #define XEHP_FF_MODE2 … #define FF_MODE2_GS_TIMER_MASK … #define FF_MODE2_GS_TIMER_224 … #define FF_MODE2_TDS_TIMER_MASK … #define FF_MODE2_TDS_TIMER_128 … #define XEHPG_INSTDONE_GEOM_SVG … #define CACHE_MODE_0_GEN7 … #define RC_OP_FLUSH_ENABLE … #define HIZ_RAW_STALL_OPT_DISABLE … #define CACHE_MODE_1 … #define MSAA_OPTIMIZATION_REDUC_DISABLE … #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE … #define GEN8_4x4_STC_OPTIMIZATION_DISABLE … #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE … #define GEN7_GT_MODE … #define GEN9_IZ_HASHING_MASK(slice) … #define GEN9_IZ_HASHING(slice, val) … /* GEN7 chicken */ #define GEN7_COMMON_SLICE_CHICKEN1 … #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC … #define GEN9_RHWO_OPTIMIZATION_DISABLE … #define COMMON_SLICE_CHICKEN2 … #define GEN9_PBE_COMPRESSED_HASH_SELECTION … #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE … #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION … #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE … #define HIZ_CHICKEN … #define CHV_HZ_8X8_MODE_IN_1X … #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE … #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE … #define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE … #define XEHP_CULLBIT2 … #define GEN8_L3CNTLREG … #define GEN8_ERRDETBCTRL … #define XEHP_PSS_MODE2 … #define SCOREBOARD_STALL_FLUSH_CONTROL … #define XEHP_PSS_CHICKEN … #define FD_END_COLLECT … #define GEN7_SC_INSTDONE … #define GEN12_SC_INSTDONE_EXTRA … #define GEN12_SC_INSTDONE_EXTRA2 … /* GEN8 chicken */ #define HDC_CHICKEN0 … #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE … #define HDC_FENCE_DEST_SLM_DISABLE … #define HDC_DONOT_FETCH_MEM_WHEN_MASKED … #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT … #define HDC_FORCE_NON_COHERENT … #define HDC_BARRIER_PERFORMANCE_DISABLE … #define COMMON_SLICE_CHICKEN4 … #define DISABLE_TDC_LOAD_BALANCING_CALC … #define GEN8_HDC_CHICKEN1 … #define GEN11_COMMON_SLICE_CHICKEN3 … #define XEHP_COMMON_SLICE_CHICKEN3 … #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN … #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE … #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC … #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE … #define GEN9_SLICE_COMMON_ECO_CHICKEN1 … #define XEHP_SLICE_COMMON_ECO_CHICKEN1 … #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE … #define GEN11_STATE_CACHE_REDIRECT_TO_CS … #define GEN9_SLICE_PGCTL_ACK(slice) … #define GEN10_SLICE_PGCTL_ACK(slice) … #define GEN9_PGCTL_SLICE_ACK … #define GEN9_PGCTL_SS_ACK(subslice) … #define GEN10_PGCTL_VALID_SS_MASK(slice) … #define GEN9_SS01_EU_PGCTL_ACK(slice) … #define GEN10_SS01_EU_PGCTL_ACK(slice) … #define GEN9_SS23_EU_PGCTL_ACK(slice) … #define GEN10_SS23_EU_PGCTL_ACK(slice) … #define GEN9_PGCTL_SSA_EU08_ACK … #define GEN9_PGCTL_SSA_EU19_ACK … #define GEN9_PGCTL_SSA_EU210_ACK … #define GEN9_PGCTL_SSA_EU311_ACK … #define GEN9_PGCTL_SSB_EU08_ACK … #define GEN9_PGCTL_SSB_EU19_ACK … #define GEN9_PGCTL_SSB_EU210_ACK … #define GEN9_PGCTL_SSB_EU311_ACK … #define VF_PREEMPTION … #define PREEMPTION_VERTEX_COUNT … #define VFG_PREEMPTION_CHICKEN … #define POLYGON_TRIFAN_LINELOOP_DISABLE … #define GEN8_RC6_CTX_INFO … #define GEN12_SQCNT1 … #define GEN12_SQCNT1_PMON_ENABLE … #define GEN12_SQCNT1_OABPC … #define GEN12_STRICT_RAR_ENABLE … #define XEHP_SQCM … #define EN_32B_ACCESS … #define MTL_GSCPSMI_BASEADDR_LSB … #define MTL_GSCPSMI_BASEADDR_MSB … #define HSW_IDICR … #define IDIHASHMSK(x) … #define GEN6_MBCUNIT_SNPCR … #define GEN6_MBC_SNPCR_SHIFT … #define GEN6_MBC_SNPCR_MASK … #define GEN6_MBC_SNPCR_MAX … #define GEN6_MBC_SNPCR_MED … #define GEN6_MBC_SNPCR_LOW … #define GEN6_MBC_SNPCR_MIN … #define VLV_G3DCTL … #define VLV_GSCKGCTL … /* WaCatErrorRejectionIssue */ #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG … #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB … #define FBC_LLC_READ_CTRL … #define FBC_LLC_FULLY_OPEN … #define GEN6_MBCTL … #define GEN6_MBCTL_ENABLE_BOOT_FETCH … #define GEN6_MBCTL_CTX_FETCH_NEEDED … #define GEN6_MBCTL_BME_UPDATE_ENABLE … #define GEN6_MBCTL_MAE_UPDATE_ENABLE … #define GEN6_MBCTL_BOOT_FETCH_MECH … /* Fuse readout registers for GT */ #define XEHP_FUSE4 … #define GT_L3_EXC_MASK … #define GEN10_MIRROR_FUSE3 … #define GEN10_L3BANK_PAIR_COUNT … #define GEN10_L3BANK_MASK … /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ #define GEN12_MAX_MSLICES … #define GEN12_MEML3_EN_MASK … #define HSW_PAVP_FUSE1 … #define XEHP_SFC_ENABLE_MASK … #define HSW_F1_EU_DIS_MASK … #define HSW_F1_EU_DIS_10EUS … #define HSW_F1_EU_DIS_8EUS … #define HSW_F1_EU_DIS_6EUS … #define GEN8_FUSE2 … #define GEN8_F2_SS_DIS_SHIFT … #define GEN8_F2_SS_DIS_MASK … #define GEN8_F2_S_ENA_SHIFT … #define GEN8_F2_S_ENA_MASK … #define GEN9_F2_SS_DIS_SHIFT … #define GEN9_F2_SS_DIS_MASK … #define GEN10_F2_S_ENA_SHIFT … #define GEN10_F2_S_ENA_MASK … #define GEN10_F2_SS_DIS_SHIFT … #define GEN10_F2_SS_DIS_MASK … #define GEN8_EU_DISABLE0 … #define GEN9_EU_DISABLE(slice) … #define GEN11_EU_DISABLE … #define GEN8_EU_DIS0_S0_MASK … #define GEN8_EU_DIS0_S1_SHIFT … #define GEN8_EU_DIS0_S1_MASK … #define GEN11_EU_DIS_MASK … #define XEHP_EU_ENABLE … #define XEHP_EU_ENA_MASK … #define GEN8_EU_DISABLE1 … #define GEN8_EU_DIS1_S1_MASK … #define GEN8_EU_DIS1_S2_SHIFT … #define GEN8_EU_DIS1_S2_MASK … #define GEN11_GT_SLICE_ENABLE … #define GEN11_GT_S_ENA_MASK … #define GEN8_EU_DISABLE2 … #define GEN8_EU_DIS2_S2_MASK … #define GEN11_GT_SUBSLICE_DISABLE … #define GEN12_GT_GEOMETRY_DSS_ENABLE … #define GEN10_EU_DISABLE3 … #define GEN10_EU_DIS_SS_MASK … #define GEN11_GT_VEBOX_VDBOX_DISABLE … #define GEN11_GT_VDBOX_DISABLE_MASK … #define GEN11_GT_VEBOX_DISABLE_SHIFT … #define GEN11_GT_VEBOX_DISABLE_MASK … #define GEN12_GT_COMPUTE_DSS_ENABLE … #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT … #define GEN6_UCGCTL1 … #define GEN6_GAMUNIT_CLOCK_GATE_DISABLE … #define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE … #define GEN6_BLBUNIT_CLOCK_GATE_DISABLE … #define GEN6_CSUNIT_CLOCK_GATE_DISABLE … #define GEN6_UCGCTL2 … #define GEN6_VFUNIT_CLOCK_GATE_DISABLE … #define GEN7_VDSUNIT_CLOCK_GATE_DISABLE … #define GEN7_TDLUNIT_CLOCK_GATE_DISABLE … #define GEN6_RCZUNIT_CLOCK_GATE_DISABLE … #define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE … #define GEN6_RCCUNIT_CLOCK_GATE_DISABLE … #define GEN6_UCGCTL3 … #define GEN6_OACSUNIT_CLOCK_GATE_DISABLE … #define GEN7_UCGCTL4 … #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE … #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE … #define GEN6_RCGCTL1 … #define GEN6_RCGCTL2 … #define GEN6_GDRST … #define GEN6_GRDOM_FULL … #define GEN6_GRDOM_RENDER … #define GEN6_GRDOM_MEDIA … #define GEN6_GRDOM_BLT … #define GEN6_GRDOM_VECS … #define GEN9_GRDOM_GUC … #define GEN8_GRDOM_MEDIA2 … /* GEN11 changed all bit defs except for FULL & RENDER */ #define GEN11_GRDOM_FULL … #define GEN11_GRDOM_RENDER … #define XEHPC_GRDOM_BLT8 … #define XEHPC_GRDOM_BLT7 … #define XEHPC_GRDOM_BLT6 … #define XEHPC_GRDOM_BLT5 … #define XEHPC_GRDOM_BLT4 … #define XEHPC_GRDOM_BLT3 … #define XEHPC_GRDOM_BLT2 … #define XEHPC_GRDOM_BLT1 … #define GEN12_GRDOM_GSC … #define GEN11_GRDOM_SFC3 … #define GEN11_GRDOM_SFC2 … #define GEN11_GRDOM_SFC1 … #define GEN11_GRDOM_SFC0 … #define GEN11_GRDOM_VECS4 … #define GEN11_GRDOM_VECS3 … #define GEN11_GRDOM_VECS2 … #define GEN11_GRDOM_VECS … #define GEN11_GRDOM_MEDIA8 … #define GEN11_GRDOM_MEDIA7 … #define GEN11_GRDOM_MEDIA6 … #define GEN11_GRDOM_MEDIA5 … #define GEN11_GRDOM_MEDIA4 … #define GEN11_GRDOM_MEDIA3 … #define GEN11_GRDOM_MEDIA2 … #define GEN11_GRDOM_MEDIA … #define GEN11_GRDOM_GUC … #define GEN11_GRDOM_BLT … #define GEN11_VCS_SFC_RESET_BIT(instance) … #define GEN11_VECS_SFC_RESET_BIT(instance) … #define GEN6_RSTCTL … #define GEN7_MISCCPCTL … #define GEN7_DOP_CLOCK_GATE_ENABLE … #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE … #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE … #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE … #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE … #define GEN8_UCGCTL6 … #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE … #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE … #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ … #define UNSLCGCTL9430 … #define MSQDUNIT_CLKGATE_DIS … #define UNSLICE_UNIT_LEVEL_CLKGATE … #define VFUNIT_CLKGATE_DIS … #define CG3DDISCFEG_CLKGATE_DIS … #define GAMEDIA_CLKGATE_DIS … #define HSUNIT_CLKGATE_DIS … #define VSUNIT_CLKGATE_DIS … #define GEN11_SLICE_UNIT_LEVEL_CLKGATE … #define XEHP_SLICE_UNIT_LEVEL_CLKGATE … #define SARBUNIT_CLKGATE_DIS … #define RCCUNIT_CLKGATE_DIS … #define MSCUNIT_CLKGATE_DIS … #define NODEDSS_CLKGATE_DIS … #define L3_CLKGATE_DIS … #define L3_CR2X_CLKGATE_DIS … #define UNSLICE_UNIT_LEVEL_CLKGATE2 … #define VSUNIT_CLKGATE_DIS_TGL … #define PSDUNIT_CLKGATE_DIS … #define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE … #define DSS_ROUTER_CLKGATE_DIS … #define GWUNIT_CLKGATE_DIS … #define SUBSLICE_UNIT_LEVEL_CLKGATE2 … #define CPSSUNIT_CLKGATE_DIS … #define SSMCGCTL9530 … #define RTFUNIT_CLKGATE_DIS … #define GEN10_DFR_RATIO_EN_AND_CHICKEN … #define DFR_DISABLE … #define MICRO_BP0_0 … #define MICRO_BP0_2 … #define MICRO_BP0_1 … #define MICRO_BP1_0 … #define MICRO_BP1_2 … #define MICRO_BP1_1 … #define MICRO_BP2_0 … #define MICRO_BP2_2 … #define MICRO_BP2_1 … #define MICRO_BP3_0 … #define MICRO_BP3_2 … #define MICRO_BP3_1 … #define MICRO_BP_TRIGGER … #define MICRO_BP3_COUNT_STATUS01 … #define MICRO_BP3_COUNT_STATUS23 … #define MICRO_BP_FIRED_ARMED … #define GEN6_GFXPAUSE … #define GEN6_RPNSWREQ … #define GEN6_TURBO_DISABLE … #define GEN6_FREQUENCY(x) … #define HSW_FREQUENCY(x) … #define GEN9_FREQUENCY(x) … #define GEN6_OFFSET(x) … #define GEN6_AGGRESSIVE_TURBO … #define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT … #define GEN9_IGNORE_SLICE_RATIO … #define GEN12_MEDIA_FREQ_RATIO … #define GEN6_RC_VIDEO_FREQ … #define GEN6_RC_CTL_RC6pp_ENABLE … #define GEN6_RC_CTL_RC6p_ENABLE … #define GEN6_RC_CTL_RC6_ENABLE … #define GEN6_RC_CTL_RC1e_ENABLE … #define GEN6_RC_CTL_RC7_ENABLE … #define VLV_RC_CTL_CTX_RST_PARALLEL … #define GEN7_RC_CTL_TO_MODE … #define GEN6_RC_CTL_EI_MODE(x) … #define GEN6_RC_CTL_HW_ENABLE … #define GEN6_RP_DOWN_TIMEOUT … #define GEN6_RP_INTERRUPT_LIMITS … #define GEN6_RPSTAT1 … #define GEN6_CAGF_MASK … #define HSW_CAGF_MASK … #define GEN9_CAGF_MASK … #define GEN6_RP_CONTROL … #define GEN6_RP_MEDIA_TURBO … #define GEN6_RP_MEDIA_MODE_MASK … #define GEN6_RP_MEDIA_HW_TURBO_MODE … #define GEN6_RP_MEDIA_HW_NORMAL_MODE … #define GEN6_RP_MEDIA_HW_MODE … #define GEN6_RP_MEDIA_SW_MODE … #define GEN6_RP_MEDIA_IS_GFX … #define GEN6_RP_ENABLE … #define GEN6_RP_UP_IDLE_MIN … #define GEN6_RP_UP_BUSY_AVG … #define GEN6_RP_UP_BUSY_CONT … #define GEN6_RP_DOWN_IDLE_AVG … #define GEN6_RP_DOWN_IDLE_CONT … #define GEN6_RPSWCTL_SHIFT … #define GEN9_RPSWCTL_ENABLE … #define GEN9_RPSWCTL_DISABLE … #define GEN6_RP_UP_THRESHOLD … #define GEN6_RP_DOWN_THRESHOLD … #define GEN6_RP_CUR_UP_EI … #define GEN6_RP_EI_MASK … #define GEN6_CURICONT_MASK … #define GEN6_RP_CUR_UP … #define GEN6_CURBSYTAVG_MASK … #define GEN6_RP_PREV_UP … #define GEN6_RP_CUR_DOWN_EI … #define GEN6_CURIAVG_MASK … #define GEN6_RP_CUR_DOWN … #define GEN6_RP_PREV_DOWN … #define GEN6_RP_UP_EI … #define GEN6_RP_DOWN_EI … #define GEN6_RP_IDLE_HYSTERSIS … #define GEN6_RPDEUHWTC … #define GEN6_RPDEUC … #define GEN6_RPDEUCSW … #define GEN6_RC_CONTROL … #define GEN6_RC_STATE … #define RC_SW_TARGET_STATE_SHIFT … #define RC_SW_TARGET_STATE_MASK … #define GEN6_RC1_WAKE_RATE_LIMIT … #define GEN6_RC6_WAKE_RATE_LIMIT … #define GEN6_RC6pp_WAKE_RATE_LIMIT … #define GEN10_MEDIA_WAKE_RATE_LIMIT … #define GEN6_RC_EVALUATION_INTERVAL … #define GEN6_RC_IDLE_HYSTERSIS … #define GEN6_RC_SLEEP … #define GEN6_RCUBMABDTMR … #define GEN6_RC1e_THRESHOLD … #define GEN6_RC6_THRESHOLD … #define GEN6_RC6p_THRESHOLD … #define VLV_RCEDATA … #define GEN6_RC6pp_THRESHOLD … #define GEN9_MEDIA_PG_IDLE_HYSTERESIS … #define GEN9_RENDER_PG_IDLE_HYSTERESIS … #define GEN6_PMINTRMSK … #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC … #define ARAT_EXPIRED_INTRMSK … #define GEN8_MISC_CTRL0 … #define ECOBUS … #define FORCEWAKE_MT_ENABLE … #define FORCEWAKE_MT … #define FORCEWAKE_GT_GEN9 … #define FORCEWAKE … #define VLV_SPAREG2H … #define GEN9_PG_ENABLE … #define GEN9_RENDER_PG_ENABLE … #define GEN9_MEDIA_PG_ENABLE … #define GEN11_MEDIA_SAMPLER_PG_ENABLE … #define VDN_HCP_POWERGATE_ENABLE(n) … #define VDN_MFX_POWERGATE_ENABLE(n) … #define GEN8_PUSHBUS_CONTROL … #define GEN8_PUSHBUS_ENABLE … #define GEN8_PUSHBUS_SHIFT … /* GPM unit config (Gen9+) */ #define CTC_MODE … #define CTC_SOURCE_PARAMETER_MASK … #define CTC_SOURCE_CRYSTAL_CLOCK … #define CTC_SOURCE_DIVIDE_LOGIC … #define CTC_SHIFT_PARAMETER_SHIFT … #define CTC_SHIFT_PARAMETER_MASK … /* GPM MSG_IDLE */ #define MSG_IDLE_CS … #define MSG_IDLE_VCS0 … #define MSG_IDLE_VCS1 … #define MSG_IDLE_BCS … #define MSG_IDLE_VECS0 … #define MSG_IDLE_VCS2 … #define MSG_IDLE_VCS3 … #define MSG_IDLE_VCS4 … #define MSG_IDLE_VCS5 … #define MSG_IDLE_VCS6 … #define MSG_IDLE_VCS7 … #define MSG_IDLE_VECS1 … #define MSG_IDLE_VECS2 … #define MSG_IDLE_VECS3 … #define MSG_IDLE_FW_MASK … #define MSG_IDLE_FW_SHIFT … #define RC_PSMI_CTRL_GSCCS … #define IDLE_MSG_DISABLE … #define PWRCTX_MAXCNT_GSCCS … #define FORCEWAKE_MEDIA_GEN9 … #define FORCEWAKE_RENDER_GEN9 … #define VLV_PWRDWNUPCTL … #define GEN9_PWRGT_DOMAIN_STATUS … #define GEN9_PWRGT_MEDIA_STATUS_MASK … #define GEN9_PWRGT_RENDER_STATUS_MASK … #define MISC_STATUS0 … #define MISC_STATUS1 … #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) … #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) … #define FORCEWAKE_REQ_GSC … #define CHV_POWER_SS0_SIG1 … #define CHV_POWER_SS0_SIG2 … #define CHV_POWER_SS1_SIG1 … #define CHV_SS_PG_ENABLE … #define CHV_EU08_PG_ENABLE … #define CHV_EU19_PG_ENABLE … #define CHV_EU210_PG_ENABLE … #define CHV_POWER_SS1_SIG2 … #define CHV_EU311_PG_ENABLE … #define GEN7_SARCHKMD … #define GEN7_DISABLE_DEMAND_PREFETCH … #define GEN7_DISABLE_SAMPLER_PREFETCH … #define GEN8_GARBCNTL … #define GEN11_ARBITRATION_PRIO_ORDER_MASK … #define GEN12_BUS_HASH_CTL_BIT_EXC … #define GEN9_GAPS_TSV_CREDIT_DISABLE … #define GEN11_HASH_CTRL_EXCL_MASK … #define GEN11_HASH_CTRL_EXCL_BIT0 … #define GEN9_SCRATCH_LNCF1 … #define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE … #define GEN7_L3SQCREG1 … #define VLV_B0_WA_L3SQCREG1_VALUE … #define GEN7_L3CNTLREG1 … #define GEN7_WA_FOR_GEN7_L3_CONTROL … #define GEN7_L3AGDIS … #define GEN7_L3CNTLREG2 … /* MOCS (Memory Object Control State) registers */ #define GEN9_LNCFCMOCS(i) … #define XEHP_LNCFCMOCS(i) … #define LNCFCMOCS_REG_COUNT … #define GEN7_L3CNTLREG3 … #define GEN7_L3_CHICKEN_MODE_REGISTER … #define GEN7_WA_L3_CHICKEN_MODE … #define GEN7_L3SQCREG4 … #define L3SQ_URB_READ_CAM_MATCH_DISABLE … #define HSW_SCRATCH1 … #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE … #define GEN7_L3LOG(slice, i) … #define GEN7_L3LOG_SIZE … #define XEHP_L3NODEARBCFG … #define XEHP_LNESPARE … #define GEN8_L3SQCREG1 … /* * Note that on CHV the following has an off-by-one error wrt. to BSpec. * Using the formula in BSpec leads to a hang, while the formula here works * fine and matches the formulas for all other platforms. A BSpec change * request has been filed to clarify this. */ #define L3_GENERAL_PRIO_CREDITS(x) … #define L3_HIGH_PRIO_CREDITS(x) … #define L3_PRIO_CREDITS_MASK … #define GEN8_L3SQCREG4 … #define GEN11_LQSC_CLEAN_EVICT_DISABLE … #define GEN8_LQSC_RO_PERF_DIS … #define GEN8_LQSC_FLUSH_COHERENT_LINES … #define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE … #define GEN9_SCRATCH1 … #define EVICTION_PERF_FIX_ENABLE … #define BDW_SCRATCH1 … #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE … #define GEN11_SCRATCH2 … #define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE … #define XEHP_L3SQCREG5 … #define L3_PWM_TIMER_INIT_VAL_MASK … #define XEHP_L3SCQREG7 … #define BLEND_FILL_CACHING_OPT_DIS … #define GEN11_GLBLINVL … #define GEN11_BANK_HASH_ADDR_EXCL_MASK … #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 … #define GEN11_LSN_UNSLCVC … #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC … #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC … #define GUCPMTIMESTAMP … #define __GEN9_RCS0_MOCS0 … #define GEN9_GFX_MOCS(i) … #define __GEN9_VCS0_MOCS0 … #define GEN9_MFX0_MOCS(i) … #define __GEN9_VCS1_MOCS0 … #define GEN9_MFX1_MOCS(i) … #define __GEN9_VECS0_MOCS0 … #define GEN9_VEBOX_MOCS(i) … #define __GEN9_BCS0_MOCS0 … #define GEN9_BLT_MOCS(i) … #define GEN12_FAULT_TLB_DATA0 … #define XEHP_FAULT_TLB_DATA0 … #define GEN12_FAULT_TLB_DATA1 … #define XEHP_FAULT_TLB_DATA1 … #define FAULT_VA_HIGH_BITS … #define FAULT_GTT_SEL … #define GEN12_RING_FAULT_REG … #define XEHP_RING_FAULT_REG … #define XELPMP_RING_FAULT_REG … #define GEN8_RING_FAULT_ENGINE_ID(x) … #define RING_FAULT_GTTSEL_MASK … #define RING_FAULT_SRCID(x) … #define RING_FAULT_FAULT_TYPE(x) … #define RING_FAULT_VALID … #define GEN12_GFX_TLB_INV_CR … #define XEHP_GFX_TLB_INV_CR … #define GEN12_VD_TLB_INV_CR … #define XEHP_VD_TLB_INV_CR … #define GEN12_VE_TLB_INV_CR … #define XEHP_VE_TLB_INV_CR … #define GEN12_BLT_TLB_INV_CR … #define XEHP_BLT_TLB_INV_CR … #define GEN12_COMPCTX_TLB_INV_CR … #define XEHP_COMPCTX_TLB_INV_CR … #define XELPMP_GSC_TLB_INV_CR … #define RENDER_MOD_CTRL … #define COMP_MOD_CTRL … #define XELPMP_GSC_MOD_CTRL … #define XEHP_VDBX_MOD_CTRL … #define XELPMP_VDBX_MOD_CTRL … #define XEHP_VEBX_MOD_CTRL … #define XELPMP_VEBX_MOD_CTRL … #define FORCE_MISS_FTLB … #define XEHP_GAMSTLB_CTRL … #define CONTROL_BLOCK_CLKGATE_DIS … #define EGRESS_BLOCK_CLKGATE_DIS … #define TAG_BLOCK_CLKGATE_DIS … #define XEHP_GAMCNTRL_CTRL … #define INVALIDATION_BROADCAST_MODE_DIS … #define GLOBAL_INVALIDATION_MODE … #define GEN12_GAM_DONE … #define GEN7_HALF_SLICE_CHICKEN1 … #define GEN8_HALF_SLICE_CHICKEN1 … #define GEN7_MAX_PS_THREAD_DEP … #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE … #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE … #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE … #define GEN7_SAMPLER_INSTDONE … #define GEN8_SAMPLER_INSTDONE … #define GEN7_ROW_INSTDONE … #define GEN8_ROW_INSTDONE … #define HALF_SLICE_CHICKEN2 … #define GEN8_ST_PO_DISABLE … #define HSW_HALF_SLICE_CHICKEN3 … #define GEN8_HALF_SLICE_CHICKEN3 … #define HSW_SAMPLE_C_PERFORMANCE … #define GEN8_CENTROID_PIXEL_OPT_DIS … #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC … #define GEN8_SAMPLER_POWER_BYPASS_DIS … #define GEN9_HALF_SLICE_CHICKEN5 … #define GEN9_DG_MIRROR_FIX_ENABLE … #define GEN9_CCS_TLB_PREFETCH_ENABLE … #define GEN10_SAMPLER_MODE … #define ENABLE_SMALLPL … #define SC_DISABLE_POWER_OPTIMIZATION_EBB … #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG … #define MTL_DISABLE_SAMPLER_SC_OOO … #define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE … #define GEN9_HALF_SLICE_CHICKEN7 … #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA … #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR … #define GEN9_ENABLE_YV12_BUGFIX … #define GEN9_ENABLE_GPGPU_PREEMPTION … #define GEN10_CACHE_MODE_SS … #define ENABLE_EU_COUNT_FOR_TDL_FLUSH … #define DISABLE_ECC … #define FLOAT_BLEND_OPTIMIZATION_ENABLE … /* * We have both ENABLE and DISABLE defines below using the same bit because the * meaning depends on the target platform. There are no platform prefix for them * because different steppings of DG2 pick one or the other semantics. */ #define ENABLE_PREFETCH_INTO_IC … #define DISABLE_PREFETCH_INTO_IC … #define EU_PERF_CNTL0 … #define EU_PERF_CNTL4 … #define GEN9_ROW_CHICKEN4 … #define XEHP_DIS_BBL_SYSPIPE … #define GEN12_DISABLE_TDL_PUSH … #define GEN11_DIS_PICK_2ND_EU … #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX … #define THREAD_EX_ARB_MODE … #define THREAD_EX_ARB_MODE_RR_AFTER_DEP … #define HSW_ROW_CHICKEN3 … #define GEN9_ROW_CHICKEN3 … #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE … #define MTL_DISABLE_FIX_FOR_EOT_FLUSH … #define GEN8_ROW_CHICKEN … #define FLOW_CONTROL_ENABLE … #define UGM_BACKUP_MODE … #define MDQ_ARBITRATION_MODE … #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE … #define STALL_DOP_GATING_DISABLE … #define THROTTLE_12_5 … #define DISABLE_EARLY_EOT … #define GEN7_ROW_CHICKEN2 … #define GEN8_ROW_CHICKEN2 … #define GEN12_DISABLE_READ_SUPPRESSION … #define GEN12_DISABLE_EARLY_READ … #define GEN12_ENABLE_LARGE_GRF_MODE … #define GEN12_PUSH_CONST_DEREF_HOLD_DIS … #define XELPG_DISABLE_TDL_SVHS_GATING … #define GEN12_DISABLE_DOP_GATING … #define RT_CTRL … #define DIS_NULL_QUERY … #define STACKID_CTRL … #define STACKID_CTRL_512 … #define EU_PERF_CNTL1 … #define EU_PERF_CNTL5 … #define XEHP_HDC_CHICKEN0 … #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK … #define DIS_ATOMIC_CHAINING_TYPED_WRITES … #define ICL_HDC_MODE … #define EU_PERF_CNTL2 … #define EU_PERF_CNTL6 … #define EU_PERF_CNTL3 … #define LSC_CHICKEN_BIT_0 … #define DISABLE_D8_D16_COASLESCE … #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT … #define LSC_CHICKEN_BIT_0_UDW … #define UGM_FRAGMENT_THRESHOLD_TO_3 … #define DIS_CHAIN_2XSIMD8 … #define FORCE_SLM_FENCE_SCOPE_TO_TILE … #define FORCE_UGM_FENCE_SCOPE_TO_TILE … #define MAXREQS_PER_BANK … #define DISABLE_128B_EVICTION_COMMAND_UDW … #define SARB_CHICKEN1 … #define COMP_CKN_IN … #define GEN7_ROW_CHICKEN2_GT2 … #define DOP_CLOCK_GATING_DISABLE … #define PUSH_CONSTANT_DEREF_DISABLE … #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE … #define __GEN11_VCS2_MOCS0 … #define GEN11_MFX2_MOCS(i) … #define CRSTANDVID … #define PXVFREQ(fstart) … #define PXVFREQ_PX_MASK … #define PXVFREQ_PX_SHIFT … #define VIDFREQ_BASE … #define VIDFREQ1 … #define VIDFREQ2 … #define VIDFREQ3 … #define VIDFREQ4 … #define VIDFREQ_P0_MASK … #define VIDFREQ_P0_SHIFT … #define VIDFREQ_P0_CSCLK_MASK … #define VIDFREQ_P0_CSCLK_SHIFT … #define VIDFREQ_P0_CRCLK_MASK … #define VIDFREQ_P0_CRCLK_SHIFT … #define VIDFREQ_P1_MASK … #define VIDFREQ_P1_SHIFT … #define VIDFREQ_P1_CSCLK_MASK … #define VIDFREQ_P1_CSCLK_SHIFT … #define VIDFREQ_P1_CRCLK_MASK … #define INTTOEXT_BASE … #define INTTOEXT_MAP3_SHIFT … #define INTTOEXT_MAP3_MASK … #define INTTOEXT_MAP2_SHIFT … #define INTTOEXT_MAP2_MASK … #define INTTOEXT_MAP1_SHIFT … #define INTTOEXT_MAP1_MASK … #define INTTOEXT_MAP0_SHIFT … #define INTTOEXT_MAP0_MASK … #define MEMSWCTL … #define MEMCTL_CMD_MASK … #define MEMCTL_CMD_SHIFT … #define MEMCTL_CMD_RCLK_OFF … #define MEMCTL_CMD_RCLK_ON … #define MEMCTL_CMD_CHFREQ … #define MEMCTL_CMD_CHVID … #define MEMCTL_CMD_VMMOFF … #define MEMCTL_CMD_VMMON … #define MEMCTL_CMD_STS … #define MEMCTL_FREQ_MASK … #define MEMCTL_FREQ_SHIFT … #define MEMCTL_SFCAVM … #define MEMCTL_TGT_VID_MASK … #define MEMIHYST … #define MEMINTREN … #define MEMINT_RSEXIT_EN … #define MEMINT_CX_SUPR_EN … #define MEMINT_CONT_BUSY_EN … #define MEMINT_AVG_BUSY_EN … #define MEMINT_EVAL_CHG_EN … #define MEMINT_MON_IDLE_EN … #define MEMINT_UP_EVAL_EN … #define MEMINT_DOWN_EVAL_EN … #define MEMINT_SW_CMD_EN … #define MEMINTRSTR … #define MEM_RSEXIT_MASK … #define MEM_RSEXIT_SHIFT … #define MEM_CONT_BUSY_MASK … #define MEM_CONT_BUSY_SHIFT … #define MEM_AVG_BUSY_MASK … #define MEM_AVG_BUSY_SHIFT … #define MEM_EVAL_CHG_MASK … #define MEM_EVAL_BUSY_SHIFT … #define MEM_MON_IDLE_MASK … #define MEM_MON_IDLE_SHIFT … #define MEM_UP_EVAL_MASK … #define MEM_UP_EVAL_SHIFT … #define MEM_DOWN_EVAL_MASK … #define MEM_DOWN_EVAL_SHIFT … #define MEM_SW_CMD_MASK … #define MEM_INT_STEER_GFX … #define MEM_INT_STEER_CMR … #define MEM_INT_STEER_SMI … #define MEM_INT_STEER_SCI … #define MEMINTRSTS … #define MEMINT_RSEXIT … #define MEMINT_CONT_BUSY … #define MEMINT_AVG_BUSY … #define MEMINT_EVAL_CHG … #define MEMINT_MON_IDLE … #define MEMINT_UP_EVAL … #define MEMINT_DOWN_EVAL … #define MEMINT_SW_CMD … #define MEMMODECTL … #define MEMMODE_BOOST_EN … #define MEMMODE_BOOST_FREQ_MASK … #define MEMMODE_BOOST_FREQ_SHIFT … #define MEMMODE_IDLE_MODE_MASK … #define MEMMODE_IDLE_MODE_SHIFT … #define MEMMODE_IDLE_MODE_EVAL … #define MEMMODE_IDLE_MODE_CONT … #define MEMMODE_HWIDLE_EN … #define MEMMODE_SWMODE_EN … #define MEMMODE_RCLK_GATE … #define MEMMODE_HW_UPDATE … #define MEMMODE_FSTART_MASK … #define MEMMODE_FSTART_SHIFT … #define MEMMODE_FMAX_MASK … #define MEMMODE_FMAX_SHIFT … #define MEMMODE_FMIN_MASK … #define RCBMAXAVG … #define MEMSWCTL2 … #define SWMEMCMD_RENDER_OFF … #define SWMEMCMD_RENDER_ON … #define SWMEMCMD_SWFREQ … #define SWMEMCMD_TARVID … #define SWMEMCMD_VRM_OFF … #define SWMEMCMD_VRM_ON … #define CMDSTS … #define SFCAVM … #define SWFREQ_MASK … #define SWFREQ_SHIFT … #define TARVID_MASK … #define MEMSTAT_CTG … #define RCBMINAVG … #define RCUPEI … #define RCDNEI … #define RSTDBYCTL … #define RS1EN … #define RS2EN … #define RS3EN … #define D3RS3EN … #define SWPROMORSX … #define RCWAKERW … #define DPRSLPVREN … #define GFXTGHYST … #define RCX_SW_EXIT … #define RSX_STATUS_MASK … #define RSX_STATUS_ON … #define RSX_STATUS_RC1 … #define RSX_STATUS_RC1E … #define RSX_STATUS_RS1 … #define RSX_STATUS_RS2 … #define RSX_STATUS_RSVD … #define RSX_STATUS_RS3 … #define RSX_STATUS_RSVD2 … #define UWRCRSXE … #define RSCRP … #define JRSC … #define RS2INC0 … #define RS1CONTSAV_MASK … #define RS1CONTSAV_NO_RS1 … #define RS1CONTSAV_RSVD … #define RS1CONTSAV_SAVE_RS1 … #define RS1CONTSAV_FULL_RS1 … #define NORMSLEXLAT_MASK … #define SLOW_RS123 … #define SLOW_RS23 … #define SLOW_RS3 … #define NORMAL_RS123 … #define RCMODE_TIMEOUT … #define IMPROMOEN … #define RCENTSYNC … #define STATELOCK … #define RS_CSTATE_MASK … #define RS_CSTATE_C367_RS1 … #define RS_CSTATE_C36_RS1_C7_RS2 … #define RS_CSTATE_RSVD … #define RS_CSTATE_C367_RS2 … #define REDSAVES … #define REDRESTORES … #define VIDCTL … #define VIDSTS … #define VIDSTART … #define MEMSTAT_ILK … #define MEMSTAT_VID_MASK … #define MEMSTAT_VID_SHIFT … #define MEMSTAT_PSTATE_MASK … #define MEMSTAT_MON_ACTV … #define MEMSTAT_SRC_CTL_MASK … #define MEMSTAT_SRC_CTL_CORE … #define MEMSTAT_SRC_CTL_TRB … #define MEMSTAT_SRC_CTL_THM … #define MEMSTAT_SRC_CTL_STDBY … #define PMMISC … #define MCPPCE_EN … #define SDEW … #define CSIEW0 … #define CSIEW1 … #define CSIEW2 … #define PEW(i) … #define DEW(i) … #define MCHAFE … #define CSIEC … #define DMIEC … #define DDREC … #define PEG0EC … #define PEG1EC … #define GFXEC … #define INTTOEXT_BASE_ILK … #define RPPREVBSYTUPAVG … #define RCPREVBSYTUPAVG … #define RCPREVBSYTDNAVG … #define RPPREVBSYTDNAVG … #define ECR … #define ECR_GPFE … #define ECR_IMONE … #define ECR_CAP_MASK … #define OGW0 … #define OGW1 … #define EG0 … #define EG1 … #define EG2 … #define EG3 … #define EG4 … #define EG5 … #define EG6 … #define EG7 … #define PXW(i) … #define PXWL(i) … #define LCFUSE02 … #define LCFUSE_HIV_MASK … #define GAC_ECO_BITS … #define ECOBITS_SNB_BIT … #define ECOBITS_PPGTT_CACHE64B … #define ECOBITS_PPGTT_CACHE4B … #define GEN12_RCU_MODE … #define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE … #define GEN12_RCU_MODE_CCS_ENABLE … #define XEHP_CCS_MODE … #define XEHP_CCS_MODE_CSLICE_MASK … #define XEHP_CCS_MODE_CSLICE_WIDTH … #define XEHP_CCS_MODE_CSLICE(cslice, ccs) … #define CHV_FUSE_GT … #define CHV_FGT_DISABLE_SS0 … #define CHV_FGT_DISABLE_SS1 … #define CHV_FGT_EU_DIS_SS0_R0_SHIFT … #define CHV_FGT_EU_DIS_SS0_R0_MASK … #define CHV_FGT_EU_DIS_SS0_R1_SHIFT … #define CHV_FGT_EU_DIS_SS0_R1_MASK … #define CHV_FGT_EU_DIS_SS1_R0_SHIFT … #define CHV_FGT_EU_DIS_SS1_R0_MASK … #define CHV_FGT_EU_DIS_SS1_R1_SHIFT … #define CHV_FGT_EU_DIS_SS1_R1_MASK … #define BCS_SWCTRL … #define BCS_SRC_Y … #define BCS_DST_Y … #define GAB_CTL … #define GAB_CTL_CONT_AFTER_PAGEFAULT … #define GEN6_PMISR … #define GEN6_PMIMR … #define GEN6_PMIIR … #define GEN6_PMIER … #define GEN6_PM_MBOX_EVENT … #define GEN6_PM_THERMAL_EVENT … /* * For Gen11 these are in the upper word of the GPM_WGBOXPERF * registers. Shifting is handled on accessing the imr and ier. */ #define GEN6_PM_RP_DOWN_TIMEOUT … #define GEN6_PM_RP_UP_THRESHOLD … #define GEN6_PM_RP_DOWN_THRESHOLD … #define GEN6_PM_RP_UP_EI_EXPIRED … #define GEN6_PM_RP_DOWN_EI_EXPIRED … #define GEN6_PM_RPS_EVENTS … #define GEN7_GT_SCRATCH(i) … #define GEN7_GT_SCRATCH_REG_NUM … #define GFX_FLSH_CNTL_GEN6 … #define GFX_FLSH_CNTL_EN … #define GTFIFODBG … #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV … #define GT_FIFO_FREE_ENTRIES_CHV … #define GT_FIFO_SBDROPERR … #define GT_FIFO_BLOBDROPERR … #define GT_FIFO_SB_READ_ABORTERR … #define GT_FIFO_DROPERR … #define GT_FIFO_OVFERR … #define GT_FIFO_IAWRERR … #define GT_FIFO_IARDERR … #define GTFIFOCTL … #define GT_FIFO_FREE_ENTRIES_MASK … #define GT_FIFO_NUM_RESERVED_ENTRIES … #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL … #define GT_FIFO_CTL_RC6_POLICY_STALL … #define FORCEWAKE_MT_ACK … #define FORCEWAKE_ACK_HSW … #define FORCEWAKE_ACK_GT_GEN9 … #define FORCEWAKE_KERNEL … #define FORCEWAKE_USER … #define FORCEWAKE_KERNEL_FALLBACK … #define FORCEWAKE_ACK … #define VLV_GTLC_WAKE_CTRL … #define VLV_GTLC_RENDER_CTX_EXISTS … #define VLV_GTLC_MEDIA_CTX_EXISTS … #define VLV_GTLC_ALLOWWAKEREQ … #define VLV_GTLC_PW_STATUS … #define VLV_GTLC_ALLOWWAKEACK … #define VLV_GTLC_ALLOWWAKEERR … #define VLV_GTLC_PW_MEDIA_STATUS_MASK … #define VLV_GTLC_PW_RENDER_STATUS_MASK … #define VLV_GTLC_SURVIVABILITY_REG … #define VLV_GFX_CLK_STATUS_BIT … #define VLV_GFX_CLK_FORCE_ON_BIT … #define FORCEWAKE_VLV … #define FORCEWAKE_ACK_VLV … #define FORCEWAKE_MEDIA_VLV … #define FORCEWAKE_ACK_MEDIA_VLV … #define MTL_MEDIA_MC6 … #define MTL_GT_ACTIVITY_FACTOR … #define MTL_GT_L3_EXC_MASK … #define GEN6_GT_THREAD_STATUS_REG … #define GEN6_GT_THREAD_STATUS_CORE_MASK … #define GEN6_GT_CORE_STATUS … #define GEN6_CORE_CPD_STATE_MASK … #define GEN6_RCn_MASK … #define GEN6_RC0 … #define GEN6_RC3 … #define GEN6_RC6 … #define GEN6_RC7 … #define GEN8_GT_SLICE_INFO … #define GEN8_LSLICESTAT_MASK … #define GEN6_GT_GFX_RC6_LOCKED … #define VLV_COUNTER_CONTROL … #define VLV_COUNT_RANGE_HIGH … #define VLV_MEDIA_RC0_COUNT_EN … #define VLV_RENDER_RC0_COUNT_EN … #define VLV_MEDIA_RC6_COUNT_EN … #define VLV_RENDER_RC6_COUNT_EN … #define GEN6_GT_GFX_RC6 … #define VLV_GT_MEDIA_RC6 … #define GEN6_GT_GFX_RC6p … #define GEN6_GT_GFX_RC6pp … #define VLV_RENDER_C0_COUNT … #define VLV_MEDIA_C0_COUNT … #define PCU_PWM_FAN_SPEED … #define GEN12_RPSTAT1 … #define GEN12_VOLTAGE_MASK … #define GEN12_CAGF_MASK … #define GEN11_GT_INTR_DW(x) … #define GEN11_CSME … #define GEN12_HECI_2 … #define GEN11_GUNIT … #define GEN11_GUC … #define MTL_MGUC … #define GEN11_WDPERF … #define GEN11_KCR … #define GEN11_GTPM … #define GEN11_BCS … #define XEHPC_BCS1 … #define XEHPC_BCS2 … #define XEHPC_BCS3 … #define XEHPC_BCS4 … #define XEHPC_BCS5 … #define XEHPC_BCS6 … #define XEHPC_BCS7 … #define XEHPC_BCS8 … #define GEN12_CCS3 … #define GEN12_CCS2 … #define GEN12_CCS1 … #define GEN12_CCS0 … #define GEN11_RCS0 … #define GEN11_VECS(x) … #define GEN11_VCS(x) … #define GEN11_RENDER_COPY_INTR_ENABLE … #define GEN11_VCS_VECS_INTR_ENABLE … #define GEN11_GUC_SG_INTR_ENABLE … #define ENGINE1_MASK … #define ENGINE0_MASK … #define GEN11_GPM_WGBOXPERF_INTR_ENABLE … #define GEN11_CRYPTO_RSVD_INTR_ENABLE … #define GEN11_GUNIT_CSME_INTR_ENABLE … #define GEN12_CCS_RSVD_INTR_ENABLE … #define GEN11_INTR_IDENTITY_REG(x) … #define GEN11_INTR_DATA_VALID … #define GEN11_INTR_ENGINE_CLASS(x) … #define GEN11_INTR_ENGINE_INSTANCE(x) … #define GEN11_INTR_ENGINE_INTR(x) … /* irq instances for OTHER_CLASS */ #define OTHER_GUC_INSTANCE … #define OTHER_GTPM_INSTANCE … #define OTHER_GSC_HECI_2_INSTANCE … #define OTHER_KCR_INSTANCE … #define OTHER_GSC_INSTANCE … #define OTHER_MEDIA_GUC_INSTANCE … #define OTHER_MEDIA_GTPM_INSTANCE … #define GEN11_IIR_REG_SELECTOR(x) … #define GEN11_RCS0_RSVD_INTR_MASK … #define GEN11_BCS_RSVD_INTR_MASK … #define GEN11_VCS0_VCS1_INTR_MASK … #define GEN11_VCS2_VCS3_INTR_MASK … #define GEN12_VCS4_VCS5_INTR_MASK … #define GEN12_VCS6_VCS7_INTR_MASK … #define GEN11_VECS0_VECS1_INTR_MASK … #define GEN12_VECS2_VECS3_INTR_MASK … #define GEN12_HECI2_RSVD_INTR_MASK … #define GEN11_GUC_SG_INTR_MASK … #define MTL_GUC_MGUC_INTR_MASK … #define GEN11_GPM_WGBOXPERF_INTR_MASK … #define GEN11_CRYPTO_RSVD_INTR_MASK … #define GEN11_GUNIT_CSME_INTR_MASK … #define GEN12_CCS0_CCS1_INTR_MASK … #define GEN12_CCS2_CCS3_INTR_MASK … #define XEHPC_BCS1_BCS2_INTR_MASK … #define XEHPC_BCS3_BCS4_INTR_MASK … #define XEHPC_BCS5_BCS6_INTR_MASK … #define XEHPC_BCS7_BCS8_INTR_MASK … #define GEN12_SFC_DONE(n) … /* * Standalone Media's non-engine GT registers are located at their regular GT * offsets plus 0x380000. This extra offset is stored inside the intel_uncore * structure so that the existing code can be used for both GTs without * modification. */ #define MTL_MEDIA_GSI_BASE … #endif /* __INTEL_GT_REGS__ */
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