/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2022, Linaro Ltd. * */ #ifndef _MHI_EP_INTERNAL_ #define _MHI_EP_INTERNAL_ #include <linux/bitfield.h> #include "../common.h" extern struct bus_type mhi_ep_bus_type; #define MHI_REG_OFFSET … #define BHI_REG_OFFSET … /* MHI registers */ #define EP_MHIREGLEN … #define EP_MHIVER … #define EP_MHICFG … #define EP_CHDBOFF … #define EP_ERDBOFF … #define EP_BHIOFF … #define EP_BHIEOFF … #define EP_DEBUGOFF … #define EP_MHICTRL … #define EP_MHISTATUS … #define EP_CCABAP_LOWER … #define EP_CCABAP_HIGHER … #define EP_ECABAP_LOWER … #define EP_ECABAP_HIGHER … #define EP_CRCBAP_LOWER … #define EP_CRCBAP_HIGHER … #define EP_CRDB_LOWER … #define EP_CRDB_HIGHER … #define EP_MHICTRLBASE_LOWER … #define EP_MHICTRLBASE_HIGHER … #define EP_MHICTRLLIMIT_LOWER … #define EP_MHICTRLLIMIT_HIGHER … #define EP_MHIDATABASE_LOWER … #define EP_MHIDATABASE_HIGHER … #define EP_MHIDATALIMIT_LOWER … #define EP_MHIDATALIMIT_HIGHER … /* MHI BHI registers */ #define EP_BHI_INTVEC … #define EP_BHI_EXECENV … /* MHI Doorbell registers */ #define CHDB_LOWER_n(n) … #define CHDB_HIGHER_n(n) … #define ERDB_LOWER_n(n) … #define ERDB_HIGHER_n(n) … #define MHI_CTRL_INT_STATUS … #define MHI_CTRL_INT_STATUS_MSK … #define MHI_CTRL_INT_STATUS_CRDB_MSK … #define MHI_CHDB_INT_STATUS_n(n) … #define MHI_ERDB_INT_STATUS_n(n) … #define MHI_CTRL_INT_CLEAR … #define MHI_CTRL_INT_MMIO_WR_CLEAR … #define MHI_CTRL_INT_CRDB_CLEAR … #define MHI_CTRL_INT_CRDB_MHICTRL_CLEAR … #define MHI_CHDB_INT_CLEAR_n(n) … #define MHI_CHDB_INT_CLEAR_n_CLEAR_ALL … #define MHI_ERDB_INT_CLEAR_n(n) … #define MHI_ERDB_INT_CLEAR_n_CLEAR_ALL … /* * Unlike the usual "masking" convention, writing "1" to a bit in this register * enables the interrupt and writing "0" will disable it.. */ #define MHI_CTRL_INT_MASK … #define MHI_CTRL_INT_MASK_MASK … #define MHI_CTRL_MHICTRL_MASK … #define MHI_CTRL_CRDB_MASK … #define MHI_CHDB_INT_MASK_n(n) … #define MHI_CHDB_INT_MASK_n_EN_ALL … #define MHI_ERDB_INT_MASK_n(n) … #define MHI_ERDB_INT_MASK_n_EN_ALL … #define NR_OF_CMD_RINGS … #define MHI_MASK_ROWS_CH_DB … #define MHI_MASK_ROWS_EV_DB … #define MHI_MASK_CH_LEN … #define MHI_MASK_EV_LEN … /* Generic context */ struct mhi_generic_ctx { … }; enum mhi_ep_ring_type { … }; /* Ring element */ mhi_ep_ring_ctx; struct mhi_ep_ring_item { … }; struct mhi_ep_ring { … }; struct mhi_ep_cmd { … }; struct mhi_ep_event { … }; struct mhi_ep_state_transition { … }; struct mhi_ep_chan { … }; /* MHI Ring related functions */ void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type, u32 id); void mhi_ep_ring_reset(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring); int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring, union mhi_ep_ring_ctx *ctx); size_t mhi_ep_ring_addr2offset(struct mhi_ep_ring *ring, u64 ptr); int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ring_element *element); void mhi_ep_ring_inc_index(struct mhi_ep_ring *ring); int mhi_ep_update_wr_offset(struct mhi_ep_ring *ring); /* MMIO related functions */ u32 mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset); void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val); void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, u32 val); u32 mhi_ep_mmio_masked_read(struct mhi_ep_cntrl *dev, u32 offset, u32 mask); void mhi_ep_mmio_enable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_disable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_enable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_disable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_enable_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id); void mhi_ep_mmio_disable_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id); void mhi_ep_mmio_enable_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl); bool mhi_ep_mmio_read_chdb_status_interrupts(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_mask_interrupts(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_get_chc_base(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_get_erc_base(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_get_crc_base(struct mhi_ep_cntrl *mhi_cntrl); u64 mhi_ep_mmio_get_db(struct mhi_ep_ring *ring); void mhi_ep_mmio_set_env(struct mhi_ep_cntrl *mhi_cntrl, u32 value); void mhi_ep_mmio_clear_reset(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_reset(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_get_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state *state, bool *mhi_reset); void mhi_ep_mmio_init(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_mmio_update_ner(struct mhi_ep_cntrl *mhi_cntrl); /* MHI EP core functions */ int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state state); int mhi_ep_send_ee_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ee_type exec_env); bool mhi_ep_check_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state cur_mhi_state, enum mhi_state mhi_state); int mhi_ep_set_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state mhi_state); int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl); int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl); int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_handle_syserr(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl); void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl); #endif
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