/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_DP_AUX_REGS_H__ #define __INTEL_DP_AUX_REGS_H__ #include "intel_display_reg_defs.h" /* * The aux channel provides a way to talk to the signal sink for DDC etc. Max * packet size supported is 20 bytes in each direction, hence the 5 fixed data * registers */ /* * Wrapper macro to convert from aux_ch to the index used in some of the * registers. */ #define __xe2lpd_aux_ch_idx(aux_ch) … #define _DPA_AUX_CH_CTL … #define _DPB_AUX_CH_CTL … #define DP_AUX_CH_CTL(aux_ch) … #define VLV_DP_AUX_CH_CTL(aux_ch) … #define _PCH_DPB_AUX_CH_CTL … #define _PCH_DPC_AUX_CH_CTL … #define PCH_DP_AUX_CH_CTL(aux_ch) … #define _XELPDP_USBC1_AUX_CH_CTL … #define _XELPDP_USBC2_AUX_CH_CTL … #define _XELPDP_DP_AUX_CH_CTL(aux_ch) … #define XELPDP_DP_AUX_CH_CTL(i915__, aux_ch) … #define DP_AUX_CH_CTL_SEND_BUSY … #define DP_AUX_CH_CTL_DONE … #define DP_AUX_CH_CTL_INTERRUPT … #define DP_AUX_CH_CTL_TIME_OUT_ERROR … #define DP_AUX_CH_CTL_TIME_OUT_MASK … #define DP_AUX_CH_CTL_TIME_OUT_400us … #define DP_AUX_CH_CTL_TIME_OUT_600us … #define DP_AUX_CH_CTL_TIME_OUT_800us … #define DP_AUX_CH_CTL_TIME_OUT_MAX … #define DP_AUX_CH_CTL_RECEIVE_ERROR … #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK … #define DP_AUX_CH_CTL_MESSAGE_SIZE(x) … #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK … #define DP_AUX_CH_CTL_PRECHARGE_2US(x) … #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST … #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS … #define DP_AUX_CH_CTL_AUX_AKSV_SELECT … #define DP_AUX_CH_CTL_MANCHESTER_TEST … #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL … #define DP_AUX_CH_CTL_SYNC_TEST … #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL … #define DP_AUX_CH_CTL_DEGLITCH_TEST … #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL … #define DP_AUX_CH_CTL_PRECHARGE_TEST … #define DP_AUX_CH_CTL_TBT_IO … #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK … #define DP_AUX_CH_CTL_BIT_CLOCK_2X(x) … #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK … #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) … #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK … #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) … #define _DPA_AUX_CH_DATA1 … #define _DPB_AUX_CH_DATA1 … #define DP_AUX_CH_DATA(aux_ch, i) … #define VLV_DP_AUX_CH_DATA(aux_ch, i) … #define _PCH_DPB_AUX_CH_DATA1 … #define _PCH_DPC_AUX_CH_DATA1 … #define PCH_DP_AUX_CH_DATA(aux_ch, i) … #define _XELPDP_USBC1_AUX_CH_DATA1 … #define _XELPDP_USBC2_AUX_CH_DATA1 … #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) … #define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) … /* PICA Power Well Control */ #define XE2LPD_PICA_PW_CTL … #define XE2LPD_PICA_CTL_POWER_REQUEST … #define XE2LPD_PICA_CTL_POWER_STATUS … #endif /* __INTEL_DP_AUX_REGS_H__ */
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