/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_PSR_REGS_H__ #define __INTEL_PSR_REGS_H__ #include "intel_display_reg_defs.h" #include "intel_dp_aux_regs.h" #define TRANS_EXITLINE(dev_priv, trans) … #define EXITLINE_ENABLE … #define EXITLINE_MASK … #define EXITLINE_SHIFT … /* * HSW+ eDP PSR registers * * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one * instance of it */ #define HSW_SRD_CTL … #define _SRD_CTL_A … #define _SRD_CTL_EDP … #define EDP_PSR_CTL(dev_priv, tran) … #define EDP_PSR_ENABLE … #define BDW_PSR_SINGLE_FRAME … #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK … #define EDP_PSR_LINK_STANDBY … #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK … #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES … #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES … #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES … #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES … #define EDP_PSR_MAX_SLEEP_TIME_MASK … #define EDP_PSR_MAX_SLEEP_TIME(x) … #define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK … #define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) … #define EDP_PSR_SKIP_AUX_EXIT … #define EDP_PSR_TP_MASK … #define EDP_PSR_TP_TP1_TP2 … #define EDP_PSR_TP_TP1_TP3 … #define EDP_PSR_CRC_ENABLE … #define EDP_PSR_TP2_TP3_TIME_MASK … #define EDP_PSR_TP2_TP3_TIME_500us … #define EDP_PSR_TP2_TP3_TIME_100us … #define EDP_PSR_TP2_TP3_TIME_2500us … #define EDP_PSR_TP2_TP3_TIME_0us … #define EDP_PSR_TP4_TIME_MASK … #define EDP_PSR_TP4_TIME_0us … #define EDP_PSR_TP1_TIME_MASK … #define EDP_PSR_TP1_TIME_500us … #define EDP_PSR_TP1_TIME_100us … #define EDP_PSR_TP1_TIME_2500us … #define EDP_PSR_TP1_TIME_0us … #define EDP_PSR_IDLE_FRAMES_MASK … #define EDP_PSR_IDLE_FRAMES(x) … /* * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative * to transcoder and bits defined for each one as if using no shift (i.e. as if * it was for TRANSCODER_EDP) */ #define EDP_PSR_IMR … #define EDP_PSR_IIR … #define _PSR_IMR_A … #define _PSR_IIR_A … #define TRANS_PSR_IMR(dev_priv, tran) … #define TRANS_PSR_IIR(dev_priv, tran) … #define _EDP_PSR_TRANS_SHIFT(trans) … #define TGL_PSR_MASK … #define TGL_PSR_ERROR … #define TGL_PSR_POST_EXIT … #define TGL_PSR_PRE_ENTRY … #define EDP_PSR_MASK(trans) … #define EDP_PSR_ERROR(trans) … #define EDP_PSR_POST_EXIT(trans) … #define EDP_PSR_PRE_ENTRY(trans) … #define HSW_SRD_AUX_CTL … #define _SRD_AUX_CTL_A … #define _SRD_AUX_CTL_EDP … #define EDP_PSR_AUX_CTL(dev_priv, tran) … #define EDP_PSR_AUX_CTL_TIME_OUT_MASK … #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK … #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK … #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT … #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK … #define HSW_SRD_AUX_DATA(i) … #define _SRD_AUX_DATA_A … #define _SRD_AUX_DATA_EDP … #define EDP_PSR_AUX_DATA(dev_priv, tran, i) … #define HSW_SRD_STATUS … #define _SRD_STATUS_A … #define _SRD_STATUS_EDP … #define EDP_PSR_STATUS(dev_priv, tran) … #define EDP_PSR_STATUS_STATE_MASK … #define EDP_PSR_STATUS_STATE_IDLE … #define EDP_PSR_STATUS_STATE_SRDONACK … #define EDP_PSR_STATUS_STATE_SRDENT … #define EDP_PSR_STATUS_STATE_BUFOFF … #define EDP_PSR_STATUS_STATE_BUFON … #define EDP_PSR_STATUS_STATE_AUXACK … #define EDP_PSR_STATUS_STATE_SRDOFFACK … #define EDP_PSR_STATUS_LINK_MASK … #define EDP_PSR_STATUS_LINK_FULL_OFF … #define EDP_PSR_STATUS_LINK_FULL_ON … #define EDP_PSR_STATUS_LINK_STANDBY … #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK … #define EDP_PSR_STATUS_COUNT_MASK … #define EDP_PSR_STATUS_AUX_ERROR … #define EDP_PSR_STATUS_AUX_SENDING … #define EDP_PSR_STATUS_SENDING_IDLE … #define EDP_PSR_STATUS_SENDING_TP2_TP3 … #define EDP_PSR_STATUS_SENDING_TP1 … #define EDP_PSR_STATUS_IDLE_MASK … #define HSW_SRD_PERF_CNT … #define _SRD_PERF_CNT_A … #define _SRD_PERF_CNT_EDP … #define EDP_PSR_PERF_CNT(dev_priv, tran) … #define EDP_PSR_PERF_CNT_MASK … /* PSR_MASK on SKL+ */ #define HSW_SRD_DEBUG … #define _SRD_DEBUG_A … #define _SRD_DEBUG_EDP … #define EDP_PSR_DEBUG(dev_priv, tran) … #define EDP_PSR_DEBUG_MASK_MAX_SLEEP … #define EDP_PSR_DEBUG_MASK_LPSP … #define EDP_PSR_DEBUG_MASK_MEMUP … #define EDP_PSR_DEBUG_MASK_HPD … #define EDP_PSR_DEBUG_MASK_FBC_MODIFY … #define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP … #define EDP_PSR_DEBUG_MASK_HDCP_ENABLE … #define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE … #define EDP_PSR_DEBUG_MASK_CURSOR_MOVE … #define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT … #define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN … #define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN … #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE … #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN … #define EDP_PSR_DEBUG_RFB_UPDATE_SENT … #define EDP_PSR_DEBUG_ENTRY_COMPLETION … #define _PSR2_CTL_A … #define _PSR2_CTL_EDP … #define EDP_PSR2_CTL(dev_priv, tran) … #define EDP_PSR2_ENABLE … #define EDP_SU_TRACK_ENABLE … #define TGL_EDP_PSR2_BLOCK_COUNT_MASK … #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 … #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 … #define LNL_EDP_PSR2_SU_REGION_ET_ENABLE … #define EDP_Y_COORDINATE_ENABLE … #define EDP_PSR2_SU_SDP_SCANLINE … #define EDP_MAX_SU_DISABLE_TIME_MASK … #define EDP_MAX_SU_DISABLE_TIME(t) … #define EDP_PSR2_IO_BUFFER_WAKE_MASK … #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES … #define EDP_PSR2_IO_BUFFER_WAKE(lines) … #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK … #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES … #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) … #define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK … #define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES … #define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) … #define EDP_PSR2_FAST_WAKE_MASK … #define EDP_PSR2_FAST_WAKE_MAX_LINES … #define EDP_PSR2_FAST_WAKE(lines) … #define TGL_EDP_PSR2_FAST_WAKE_MASK … #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES … #define TGL_EDP_PSR2_FAST_WAKE(lines) … #define EDP_PSR2_TP2_TIME_MASK … #define EDP_PSR2_TP2_TIME_500us … #define EDP_PSR2_TP2_TIME_100us … #define EDP_PSR2_TP2_TIME_2500us … #define EDP_PSR2_TP2_TIME_50us … #define EDP_PSR2_FRAME_BEFORE_SU_MASK … #define EDP_PSR2_FRAME_BEFORE_SU(a) … #define EDP_PSR2_IDLE_FRAMES_MASK … #define EDP_PSR2_IDLE_FRAMES(x) … #define _PSR_EVENT_TRANS_A … #define _PSR_EVENT_TRANS_B … #define _PSR_EVENT_TRANS_C … #define _PSR_EVENT_TRANS_D … #define _PSR_EVENT_TRANS_EDP … #define PSR_EVENT(dev_priv, tran) … #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE … #define PSR_EVENT_PSR2_DISABLED … #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN … #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN … #define PSR_EVENT_GRAPHICS_RESET … #define PSR_EVENT_PCH_INTERRUPT … #define PSR_EVENT_MEMORY_UP … #define PSR_EVENT_FRONT_BUFFER_MODIFY … #define PSR_EVENT_WD_TIMER_EXPIRE … #define PSR_EVENT_PIPE_REGISTERS_UPDATE … #define PSR_EVENT_REGISTER_UPDATE … #define PSR_EVENT_HDCP_ENABLE … #define PSR_EVENT_KVMR_SESSION_ENABLE … #define PSR_EVENT_VBI_ENABLE … #define PSR_EVENT_LPSP_MODE_EXIT … #define PSR_EVENT_PSR_DISABLE … #define _PSR2_STATUS_A … #define _PSR2_STATUS_EDP … #define EDP_PSR2_STATUS(dev_priv, tran) … #define EDP_PSR2_STATUS_STATE_MASK … #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP … #define _PSR2_SU_STATUS_A … #define _PSR2_SU_STATUS_EDP … #define _PSR2_SU_STATUS(dev_priv, tran, index) … #define PSR2_SU_STATUS(dev_priv, tran, frame) … #define PSR2_SU_STATUS_SHIFT(frame) … #define PSR2_SU_STATUS_MASK(frame) … #define PSR2_SU_STATUS_FRAMES … #define _PSR2_MAN_TRK_CTL_A … #define _PSR2_MAN_TRK_CTL_EDP … #define PSR2_MAN_TRK_CTL(dev_priv, tran) … #define PSR2_MAN_TRK_CTL_ENABLE … #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK … #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) … #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK … #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) … #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME … #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME … #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE … #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK … #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) … #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK … #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) … #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE … #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME … #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME … /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A … #define _PIPE_SRCSZ_ERLY_TPT_B … #define PIPE_SRCSZ_ERLY_TPT(pipe) … #define _ALPM_CTL_A … #define ALPM_CTL(dev_priv, tran) … #define ALPM_CTL_ALPM_ENABLE … #define ALPM_CTL_ALPM_AUX_LESS_ENABLE … #define ALPM_CTL_LOBF_ENABLE … #define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE … #define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP … #define ALPM_CTL_RESTORE_OCCURED … #define ALPM_CTL_RESTORE_TO_SLEEP … #define ALPM_CTL_RESTORE_TO_DEEP_SLEEP … #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK … #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS … #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS … #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS … #define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS … #define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE … #define ALPM_CTL_ALPM_ENTRY_CHECK_MASK … #define ALPM_CTL_ALPM_ENTRY_CHECK(val) … #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK … #define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES … #define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) … #define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK … #define ALPM_CTL_AUX_LESS_WAKE_TIME(val) … #define _ALPM_CTL2_A … #define ALPM_CTL2(dev_priv, tran) … #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK … #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) … #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK … #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) … #define ALPM_CTL2_NUMBER_OF_LTTPR_MASK … #define ALPM_CTL2_NUMBER_OF_LTTPR(val) … #define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK … #define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) … #define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR … #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK … #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) … #define _PORT_ALPM_CTL_A … #define _PORT_ALPM_CTL_B … #define PORT_ALPM_CTL(dev_priv, port) … #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE … #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK … #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) … #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK … #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) … #define PORT_ALPM_CTL_SILENCE_PERIOD_MASK … #define PORT_ALPM_CTL_SILENCE_PERIOD(val) … #define _PORT_ALPM_LFPS_CTL_A … #define _PORT_ALPM_LFPS_CTL_B … #define PORT_ALPM_LFPS_CTL(dev_priv, port) … #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY … #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK … #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN … #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) … #define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK … #define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) … #define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK … #define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) … #define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK … #define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) … #endif /* __INTEL_PSR_REGS_H__ */
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