// SPDX-License-Identifier: GPL-2.0 /* * Meson G12A USB2 PHY driver * * Copyright (C) 2017 Martin Blumenstingl <[email protected]> * Copyright (C) 2017 Amlogic, Inc. All rights reserved * Copyright (C) 2019 BayLibre, SAS * Author: Neil Armstrong <[email protected]> */ #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #define PHY_CTRL_R0 … #define PHY_CTRL_R1 … #define PHY_CTRL_R2 … #define PHY_CTRL_R3 … #define PHY_CTRL_R3_SQUELCH_REF … #define PHY_CTRL_R3_HSDIC_REF … #define PHY_CTRL_R3_DISC_THRESH … #define PHY_CTRL_R4 … #define PHY_CTRL_R4_CALIB_CODE_7_0 … #define PHY_CTRL_R4_CALIB_CODE_15_8 … #define PHY_CTRL_R4_CALIB_CODE_23_16 … #define PHY_CTRL_R4_I_C2L_CAL_EN … #define PHY_CTRL_R4_I_C2L_CAL_RESET_N … #define PHY_CTRL_R4_I_C2L_CAL_DONE … #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN … #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 … #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 … #define PHY_CTRL_R5 … #define PHY_CTRL_R6 … #define PHY_CTRL_R7 … #define PHY_CTRL_R8 … #define PHY_CTRL_R9 … #define PHY_CTRL_R10 … #define PHY_CTRL_R11 … #define PHY_CTRL_R12 … #define PHY_CTRL_R13 … #define PHY_CTRL_R13_CUSTOM_PATTERN_19 … #define PHY_CTRL_R13_LOAD_STAT … #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS … #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET … #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT … #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL … #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN … #define PHY_CTRL_R13_I_C2L_HS_EN … #define PHY_CTRL_R13_I_C2L_FS_EN … #define PHY_CTRL_R13_I_C2L_LS_EN … #define PHY_CTRL_R13_I_C2L_HS_OE … #define PHY_CTRL_R13_I_C2L_FS_OE … #define PHY_CTRL_R13_I_C2L_HS_RX_EN … #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN … #define PHY_CTRL_R14 … #define PHY_CTRL_R14_I_RDP_EN … #define PHY_CTRL_R14_I_RPU_SW1_EN … #define PHY_CTRL_R14_I_RPU_SW2_EN … #define PHY_CTRL_R14_PG_RSTN … #define PHY_CTRL_R14_I_C2L_DATA_16_8 … #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO … #define PHY_CTRL_R14_BYPASS_CTRL_7_0 … #define PHY_CTRL_R14_BYPASS_CTRL_15_8 … #define PHY_CTRL_R15 … #define PHY_CTRL_R16 … #define PHY_CTRL_R16_MPLL_M … #define PHY_CTRL_R16_MPLL_N … #define PHY_CTRL_R16_MPLL_TDC_MODE … #define PHY_CTRL_R16_MPLL_SDM_EN … #define PHY_CTRL_R16_MPLL_LOAD … #define PHY_CTRL_R16_MPLL_DCO_SDM_EN … #define PHY_CTRL_R16_MPLL_LOCK_LONG … #define PHY_CTRL_R16_MPLL_LOCK_F … #define PHY_CTRL_R16_MPLL_FAST_LOCK … #define PHY_CTRL_R16_MPLL_EN … #define PHY_CTRL_R16_MPLL_RESET … #define PHY_CTRL_R16_MPLL_LOCK … #define PHY_CTRL_R16_MPLL_LOCK_DIG … #define PHY_CTRL_R17 … #define PHY_CTRL_R17_MPLL_FRAC_IN … #define PHY_CTRL_R17_MPLL_FIX_EN … #define PHY_CTRL_R17_MPLL_LAMBDA1 … #define PHY_CTRL_R17_MPLL_LAMBDA0 … #define PHY_CTRL_R17_MPLL_FILTER_MODE … #define PHY_CTRL_R17_MPLL_FILTER_PVT2 … #define PHY_CTRL_R17_MPLL_FILTER_PVT1 … #define PHY_CTRL_R18 … #define PHY_CTRL_R18_MPLL_LKW_SEL … #define PHY_CTRL_R18_MPLL_LK_W … #define PHY_CTRL_R18_MPLL_LK_S … #define PHY_CTRL_R18_MPLL_DCO_M_EN … #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL … #define PHY_CTRL_R18_MPLL_PFD_GAIN … #define PHY_CTRL_R18_MPLL_ROU … #define PHY_CTRL_R18_MPLL_DATA_SEL … #define PHY_CTRL_R18_MPLL_BIAS_ADJ … #define PHY_CTRL_R18_MPLL_BB_MODE … #define PHY_CTRL_R18_MPLL_ALPHA … #define PHY_CTRL_R18_MPLL_ADJ_LDO … #define PHY_CTRL_R18_MPLL_ACG_RANGE … #define PHY_CTRL_R19 … #define PHY_CTRL_R20 … #define PHY_CTRL_R20_USB2_IDDET_EN … #define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0 … #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN … #define PHY_CTRL_R20_USB2_AMON_EN … #define PHY_CTRL_R20_USB2_CAL_CODE_R5 … #define PHY_CTRL_R20_BYPASS_OTG_DET … #define PHY_CTRL_R20_USB2_DMON_EN … #define PHY_CTRL_R20_USB2_DMON_SEL_3_0 … #define PHY_CTRL_R20_USB2_EDGE_DRV_EN … #define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0 … #define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 … #define PHY_CTRL_R20_USB2_BGR_START … #define PHY_CTRL_R20_USB2_BGR_VREF_4_0 … #define PHY_CTRL_R20_USB2_BGR_DBG_1_0 … #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 … #define PHY_CTRL_R21 … #define PHY_CTRL_R21_USB2_BGR_FORCE … #define PHY_CTRL_R21_USB2_CAL_ACK_EN … #define PHY_CTRL_R21_USB2_OTG_ACA_EN … #define PHY_CTRL_R21_USB2_TX_STRG_PD … #define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 … #define PHY_CTRL_R21_BYPASS_UTMI_CNTR … #define PHY_CTRL_R21_BYPASS_UTMI_REG … #define PHY_CTRL_R22 … #define PHY_CTRL_R23 … #define RESET_COMPLETE_TIME … #define PLL_RESET_COMPLETE_TIME … enum meson_soc_id { … }; struct phy_meson_g12a_usb2_priv { … }; static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = …; static int phy_meson_g12a_usb2_init(struct phy *phy) { … } static int phy_meson_g12a_usb2_exit(struct phy *phy) { … } /* set_mode is not needed, mode setting is handled via the UTMI bus */ static const struct phy_ops phy_meson_g12a_usb2_ops = …; static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) { … } static const struct of_device_id phy_meson_g12a_usb2_of_match[] = …; MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match); static struct platform_driver phy_meson_g12a_usb2_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux