linux/drivers/phy/mediatek/phy-mtk-xsphy.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek USB3.1 gen2 xsphy Driver
 *
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Chunfeng Yun <[email protected]>
 *
 */

#include <dt-bindings/phy/phy.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>

#include "phy-mtk-io.h"

/* u2 phy banks */
#define SSUSB_SIFSLV_MISC
#define SSUSB_SIFSLV_U2FREQ
#define SSUSB_SIFSLV_U2PHY_COM

/* u3 phy shared banks */
#define SSPXTP_SIFSLV_DIG_GLB
#define SSPXTP_SIFSLV_PHYA_GLB

/* u3 phy banks */
#define SSPXTP_SIFSLV_DIG_LN_TOP
#define SSPXTP_SIFSLV_DIG_LN_TX0
#define SSPXTP_SIFSLV_DIG_LN_RX0
#define SSPXTP_SIFSLV_DIG_LN_DAIF
#define SSPXTP_SIFSLV_PHYA_LN

#define XSP_U2FREQ_FMCR0
#define P2F_RG_FREQDET_EN
#define P2F_RG_CYCLECNT

#define XSP_U2FREQ_MMONR0

#define XSP_U2FREQ_FMMONR1
#define P2F_RG_FRCK_EN
#define P2F_USB_FM_VALID

#define XSP_USBPHYACR0
#define P2A0_RG_INTR_EN

#define XSP_USBPHYACR1
#define P2A1_RG_INTR_CAL
#define P2A1_RG_VRT_SEL
#define P2A1_RG_TERM_SEL

#define XSP_USBPHYACR5
#define P2A5_RG_HSTX_SRCAL_EN
#define P2A5_RG_HSTX_SRCTRL

#define XSP_USBPHYACR6
#define P2A6_RG_BC11_SW_EN
#define P2A6_RG_OTG_VBUSCMP_EN

#define XSP_U2PHYDTM1
#define P2D_FORCE_IDDIG
#define P2D_RG_VBUSVALID
#define P2D_RG_SESSEND
#define P2D_RG_AVALID
#define P2D_RG_IDDIG

#define SSPXTP_PHYA_GLB_00
#define RG_XTP_GLB_BIAS_INTR_CTRL

#define SSPXTP_PHYA_LN_04
#define RG_XTP_LN0_TX_IMPSEL

#define SSPXTP_PHYA_LN_14
#define RG_XTP_LN0_RX_IMPSEL

#define XSP_REF_CLK
#define XSP_SLEW_RATE_COEF
#define XSP_SR_COEF_DIVISOR
#define XSP_FM_DET_CYCLE_CNT

struct xsphy_instance {};

struct mtk_xsphy {};

static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
					struct xsphy_instance *inst)
{}

static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
				 struct xsphy_instance *inst)
{}

static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
				     struct xsphy_instance *inst)
{}

static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
				      struct xsphy_instance *inst)
{}

static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
				     struct xsphy_instance *inst,
				     enum phy_mode mode)
{}

static void phy_parse_property(struct mtk_xsphy *xsphy,
				struct xsphy_instance *inst)
{}

static void u2_phy_props_set(struct mtk_xsphy *xsphy,
			     struct xsphy_instance *inst)
{}

static void u3_phy_props_set(struct mtk_xsphy *xsphy,
			     struct xsphy_instance *inst)
{}

static int mtk_phy_init(struct phy *phy)
{}

static int mtk_phy_power_on(struct phy *phy)
{}

static int mtk_phy_power_off(struct phy *phy)
{}

static int mtk_phy_exit(struct phy *phy)
{}

static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{}

static struct phy *mtk_phy_xlate(struct device *dev,
				 const struct of_phandle_args *args)
{}

static const struct phy_ops mtk_xsphy_ops =;

static const struct of_device_id mtk_xsphy_id_table[] =;
MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);

static int mtk_xsphy_probe(struct platform_device *pdev)
{}

static struct platform_driver mtk_xsphy_driver =;

module_platform_driver();

MODULE_AUTHOR();
MODULE_DESCRIPTION();
MODULE_LICENSE();