// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2023, Linaro Limited */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/iopoll.h> #include <linux/mod_devicetable.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/reset.h> #define USB_PHY_UTMI_CTRL0 … #define SLEEPM … #define OPMODE_MASK … #define OPMODE_NONDRIVING … #define USB_PHY_UTMI_CTRL5 … #define POR … #define USB_PHY_HS_PHY_CTRL_COMMON0 … #define PHY_ENABLE … #define SIDDQ_SEL … #define SIDDQ … #define RETENABLEN … #define FSEL_MASK … #define FSEL_19_2_MHZ_VAL … #define FSEL_38_4_MHZ_VAL … #define USB_PHY_CFG_CTRL_1 … #define PHY_CFG_PLL_CPBIAS_CNTRL_MASK … #define USB_PHY_CFG_CTRL_2 … #define PHY_CFG_PLL_FB_DIV_7_0_MASK … #define DIV_7_0_19_2_MHZ_VAL … #define DIV_7_0_38_4_MHZ_VAL … #define USB_PHY_CFG_CTRL_3 … #define PHY_CFG_PLL_FB_DIV_11_8_MASK … #define DIV_11_8_19_2_MHZ_VAL … #define DIV_11_8_38_4_MHZ_VAL … #define PHY_CFG_PLL_REF_DIV … #define PLL_REF_DIV_VAL … #define USB_PHY_HS_PHY_CTRL2 … #define VBUSVLDEXT0 … #define USB2_SUSPEND_N … #define USB2_SUSPEND_N_SEL … #define VBUS_DET_EXT_SEL … #define USB_PHY_CFG_CTRL_4 … #define PHY_CFG_PLL_GMP_CNTRL_MASK … #define PHY_CFG_PLL_INT_CNTRL_MASK … #define USB_PHY_CFG_CTRL_5 … #define PHY_CFG_PLL_PROP_CNTRL_MASK … #define PHY_CFG_PLL_VREF_TUNE_MASK … #define USB_PHY_CFG_CTRL_6 … #define PHY_CFG_PLL_VCO_CNTRL_MASK … #define USB_PHY_CFG_CTRL_7 … #define USB_PHY_CFG_CTRL_8 … #define PHY_CFG_TX_FSLS_VREF_TUNE_MASK … #define PHY_CFG_TX_FSLS_VREG_BYPASS … #define PHY_CFG_TX_HS_VREF_TUNE_MASK … #define PHY_CFG_TX_HS_XV_TUNE_MASK … #define USB_PHY_CFG_CTRL_9 … #define PHY_CFG_TX_PREEMP_TUNE_MASK … #define PHY_CFG_TX_RES_TUNE_MASK … #define PHY_CFG_TX_RISE_TUNE_MASK … #define PHY_CFG_RCAL_BYPASS … #define USB_PHY_CFG_CTRL_10 … #define USB_PHY_CFG0 … #define DATAPATH_CTRL_OVERRIDE_EN … #define CMN_CTRL_OVERRIDE_EN … #define UTMI_PHY_CMN_CTRL0 … #define TESTBURNIN … #define USB_PHY_FSEL_SEL … #define FSEL_SEL … #define USB_PHY_APB_ACCESS_CMD … #define RW_ACCESS … #define APB_START_CMD … #define APB_LOGIC_RESET … #define USB_PHY_APB_ACCESS_STATUS … #define ACCESS_DONE … #define TIMED_OUT … #define ACCESS_ERROR … #define ACCESS_IN_PROGRESS … #define USB_PHY_APB_ADDRESS … #define APB_REG_ADDR_MASK … #define USB_PHY_APB_WRDATA_LSB … #define APB_REG_WRDATA_7_0_MASK … #define USB_PHY_APB_WRDATA_MSB … #define APB_REG_WRDATA_15_8_MASK … #define USB_PHY_APB_RDDATA_LSB … #define APB_REG_RDDATA_7_0_MASK … #define USB_PHY_APB_RDDATA_MSB … #define APB_REG_RDDATA_15_8_MASK … static const char * const eusb2_hsphy_vreg_names[] = …; #define EUSB2_NUM_VREGS … struct qcom_snps_eusb2_hsphy { … }; static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) { … } static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, u32 mask, u32 val) { … } static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy) { … } static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy) { … } static int qcom_snps_eusb2_hsphy_init(struct phy *p) { … } static int qcom_snps_eusb2_hsphy_exit(struct phy *p) { … } static const struct phy_ops qcom_snps_eusb2_hsphy_ops = …; static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev) { … } static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = …; MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table); static struct platform_driver qcom_snps_eusb2_hsphy_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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