linux/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_
#define QCOM_PHY_QMP_QSERDES_PLL_H_

/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */
#define QSERDES_PLL_BG_TIMER …
#define QSERDES_PLL_SSC_EN_CENTER …
#define QSERDES_PLL_SSC_ADJ_PER1 …
#define QSERDES_PLL_SSC_ADJ_PER2 …
#define QSERDES_PLL_SSC_PER1 …
#define QSERDES_PLL_SSC_PER2 …
#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 …
#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 …
#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 …
#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 …
#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN …
#define QSERDES_PLL_CLK_ENABLE1 …
#define QSERDES_PLL_SYS_CLK_CTRL …
#define QSERDES_PLL_SYSCLK_BUF_ENABLE …
#define QSERDES_PLL_PLL_IVCO …
#define QSERDES_PLL_LOCK_CMP1_MODE0 …
#define QSERDES_PLL_LOCK_CMP2_MODE0 …
#define QSERDES_PLL_LOCK_CMP1_MODE1 …
#define QSERDES_PLL_LOCK_CMP2_MODE1 …
#define QSERDES_PLL_BG_TRIM …
#define QSERDES_PLL_CLK_EP_DIV_MODE0 …
#define QSERDES_PLL_CLK_EP_DIV_MODE1 …
#define QSERDES_PLL_CP_CTRL_MODE0 …
#define QSERDES_PLL_CP_CTRL_MODE1 …
#define QSERDES_PLL_PLL_RCTRL_MODE0 …
#define QSERDES_PLL_PLL_RCTRL_MODE1 …
#define QSERDES_PLL_PLL_CCTRL_MODE0 …
#define QSERDES_PLL_PLL_CCTRL_MODE1 …
#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM …
#define QSERDES_PLL_SYSCLK_EN_SEL …
#define QSERDES_PLL_RESETSM_CNTRL …
#define QSERDES_PLL_LOCK_CMP_EN …
#define QSERDES_PLL_DEC_START_MODE0 …
#define QSERDES_PLL_DEC_START_MODE1 …
#define QSERDES_PLL_DIV_FRAC_START1_MODE0 …
#define QSERDES_PLL_DIV_FRAC_START2_MODE0 …
#define QSERDES_PLL_DIV_FRAC_START3_MODE0 …
#define QSERDES_PLL_DIV_FRAC_START1_MODE1 …
#define QSERDES_PLL_DIV_FRAC_START2_MODE1 …
#define QSERDES_PLL_DIV_FRAC_START3_MODE1 …
#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 …
#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 …
#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 …
#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 …
#define QSERDES_PLL_VCO_TUNE_MAP …
#define QSERDES_PLL_VCO_TUNE1_MODE0 …
#define QSERDES_PLL_VCO_TUNE2_MODE0 …
#define QSERDES_PLL_VCO_TUNE1_MODE1 …
#define QSERDES_PLL_VCO_TUNE2_MODE1 …
#define QSERDES_PLL_VCO_TUNE_TIMER1 …
#define QSERDES_PLL_VCO_TUNE_TIMER2 …
#define QSERDES_PLL_CLK_SELECT …
#define QSERDES_PLL_HSCLK_SEL …
#define QSERDES_PLL_CORECLK_DIV …
#define QSERDES_PLL_CORE_CLK_EN …
#define QSERDES_PLL_CMN_CONFIG …
#define QSERDES_PLL_SVS_MODE_CLK_SEL …
#define QSERDES_PLL_CORECLK_DIV_MODE1 …

#endif