/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. */ #ifndef QCOM_PHY_QMP_PCS_V4_H_ #define QCOM_PHY_QMP_PCS_V4_H_ /* Only for QMP V4 PHY - USB/PCIe PCS registers */ #define QPHY_V4_PCS_SW_RESET … #define QPHY_V4_PCS_REVISION_ID0 … #define QPHY_V4_PCS_REVISION_ID1 … #define QPHY_V4_PCS_REVISION_ID2 … #define QPHY_V4_PCS_REVISION_ID3 … #define QPHY_V4_PCS_PCS_STATUS1 … #define QPHY_V4_PCS_PCS_STATUS2 … #define QPHY_V4_PCS_PCS_STATUS3 … #define QPHY_V4_PCS_PCS_STATUS4 … #define QPHY_V4_PCS_PCS_STATUS5 … #define QPHY_V4_PCS_PCS_STATUS6 … #define QPHY_V4_PCS_PCS_STATUS7 … #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS … #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS … #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS … #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS … #define QPHY_V4_PCS_POWER_DOWN_CONTROL … #define QPHY_V4_PCS_START_CONTROL … #define QPHY_V4_PCS_INSIG_SW_CTRL1 … #define QPHY_V4_PCS_INSIG_SW_CTRL2 … #define QPHY_V4_PCS_INSIG_SW_CTRL3 … #define QPHY_V4_PCS_INSIG_SW_CTRL4 … #define QPHY_V4_PCS_INSIG_SW_CTRL5 … #define QPHY_V4_PCS_INSIG_SW_CTRL6 … #define QPHY_V4_PCS_INSIG_SW_CTRL7 … #define QPHY_V4_PCS_INSIG_SW_CTRL8 … #define QPHY_V4_PCS_INSIG_MX_CTRL1 … #define QPHY_V4_PCS_INSIG_MX_CTRL2 … #define QPHY_V4_PCS_INSIG_MX_CTRL3 … #define QPHY_V4_PCS_INSIG_MX_CTRL4 … #define QPHY_V4_PCS_INSIG_MX_CTRL5 … #define QPHY_V4_PCS_INSIG_MX_CTRL7 … #define QPHY_V4_PCS_INSIG_MX_CTRL8 … #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 … #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 … #define QPHY_V4_PCS_CLAMP_ENABLE … #define QPHY_V4_PCS_POWER_STATE_CONFIG1 … #define QPHY_V4_PCS_POWER_STATE_CONFIG2 … #define QPHY_V4_PCS_FLL_CNTRL1 … #define QPHY_V4_PCS_FLL_CNTRL2 … #define QPHY_V4_PCS_FLL_CNT_VAL_L … #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL … #define QPHY_V4_PCS_FLL_MAN_CODE … #define QPHY_V4_PCS_TEST_CONTROL1 … #define QPHY_V4_PCS_TEST_CONTROL2 … #define QPHY_V4_PCS_TEST_CONTROL3 … #define QPHY_V4_PCS_TEST_CONTROL4 … #define QPHY_V4_PCS_TEST_CONTROL5 … #define QPHY_V4_PCS_TEST_CONTROL6 … #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 … #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 … #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 … #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 … #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 … #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 … #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 … #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 … #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 … #define QPHY_V4_PCS_BIST_CTRL … #define QPHY_V4_PCS_PRBS_POLY0 … #define QPHY_V4_PCS_PRBS_POLY1 … #define QPHY_V4_PCS_FIXED_PAT0 … #define QPHY_V4_PCS_FIXED_PAT1 … #define QPHY_V4_PCS_FIXED_PAT2 … #define QPHY_V4_PCS_FIXED_PAT3 … #define QPHY_V4_PCS_FIXED_PAT4 … #define QPHY_V4_PCS_FIXED_PAT5 … #define QPHY_V4_PCS_FIXED_PAT6 … #define QPHY_V4_PCS_FIXED_PAT7 … #define QPHY_V4_PCS_FIXED_PAT8 … #define QPHY_V4_PCS_FIXED_PAT9 … #define QPHY_V4_PCS_FIXED_PAT10 … #define QPHY_V4_PCS_FIXED_PAT11 … #define QPHY_V4_PCS_FIXED_PAT12 … #define QPHY_V4_PCS_FIXED_PAT13 … #define QPHY_V4_PCS_FIXED_PAT14 … #define QPHY_V4_PCS_FIXED_PAT15 … #define QPHY_V4_PCS_TXMGN_CONFIG … #define QPHY_V4_PCS_G12S1_TXMGN_V0 … #define QPHY_V4_PCS_G12S1_TXMGN_V1 … #define QPHY_V4_PCS_G12S1_TXMGN_V2 … #define QPHY_V4_PCS_G12S1_TXMGN_V3 … #define QPHY_V4_PCS_G12S1_TXMGN_V4 … #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS … #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS … #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS … #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS … #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS … #define QPHY_V4_PCS_G3S2_TXMGN_MAIN … #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS … #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB … #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB … #define QPHY_V4_PCS_G3S2_PRE_GAIN … #define QPHY_V4_PCS_G3S2_POST_GAIN … #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET … #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS … #define QPHY_V4_PCS_G3S2_POST_GAIN_RS … #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS … #define QPHY_V4_PCS_RX_SIGDET_LVL … #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL … #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L … #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H … #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 … #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 … #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK … #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L … #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H … #define QPHY_V4_PCS_TSYNC_RSYNC_TIME … #define QPHY_V4_PCS_CDR_RESET_TIME … #define QPHY_V4_PCS_TSYNC_DLY_TIME … #define QPHY_V4_PCS_ELECIDLE_DLY_SEL … #define QPHY_V4_PCS_CMN_ACK_OUT_SEL … #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 … #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 … #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 … #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 … #define QPHY_V4_PCS_PCS_TX_RX_CONFIG … #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL … #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG … #define QPHY_V4_PCS_EQ_CONFIG1 … #define QPHY_V4_PCS_EQ_CONFIG2 … #define QPHY_V4_PCS_EQ_CONFIG3 … #define QPHY_V4_PCS_EQ_CONFIG4 … #define QPHY_V4_PCS_EQ_CONFIG5 … #endif
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