// SPDX-License-Identifier: GPL-2.0+ /* * Mediatek MT7621 PCI PHY Driver * Author: Sergio Paracuellos <[email protected]> */ #include <dt-bindings/phy/phy.h> #include <linux/clk.h> #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/sys_soc.h> #define RG_PE1_PIPE_REG … #define RG_PE1_PIPE_RST … #define RG_PE1_PIPE_CMD_FRC … #define RG_P0_TO_P1_WIDTH … #define RG_PE1_H_LCDDS_REG … #define RG_PE1_H_LCDDS_PCW … #define RG_PE1_FRC_H_XTAL_REG … #define RG_PE1_FRC_H_XTAL_TYPE … #define RG_PE1_H_XTAL_TYPE … #define RG_PE1_FRC_PHY_REG … #define RG_PE1_FRC_PHY_EN … #define RG_PE1_PHY_EN … #define RG_PE1_H_PLL_REG … #define RG_PE1_H_PLL_BC … #define RG_PE1_H_PLL_BP … #define RG_PE1_H_PLL_IR … #define RG_PE1_H_PLL_IC … #define RG_PE1_H_PLL_PREDIV … #define RG_PE1_PLL_DIVEN … #define RG_PE1_H_PLL_FBKSEL_REG … #define RG_PE1_H_PLL_FBKSEL … #define RG_PE1_H_LCDDS_SSC_PRD_REG … #define RG_PE1_H_LCDDS_SSC_PRD … #define RG_PE1_H_LCDDS_SSC_DELTA_REG … #define RG_PE1_H_LCDDS_SSC_DELTA … #define RG_PE1_H_LCDDS_SSC_DELTA1 … #define RG_PE1_LCDDS_CLK_PH_INV_REG … #define RG_PE1_LCDDS_CLK_PH_INV … #define RG_PE1_H_PLL_BR_REG … #define RG_PE1_H_PLL_BR … #define RG_PE1_MSTCKDIV_REG … #define RG_PE1_MSTCKDIV … #define RG_PE1_FRC_MSTCKDIV … #define MAX_PHYS … /** * struct mt7621_pci_phy - Mt7621 Pcie PHY core * @dev: pointer to device * @regmap: kernel regmap pointer * @phy: pointer to the kernel PHY device * @sys_clk: pointer to the system XTAL clock * @port_base: base register * @has_dual_port: if the phy has dual ports. * @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst' * needs to be executed. Depends on chip revision. */ struct mt7621_pci_phy { … }; static inline void mt7621_phy_rmw(struct mt7621_pci_phy *phy, u32 reg, u32 clr, u32 set) { … } static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy) { … } static int mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy) { … } static int mt7621_pci_phy_init(struct phy *phy) { … } static int mt7621_pci_phy_power_on(struct phy *phy) { … } static int mt7621_pci_phy_power_off(struct phy *phy) { … } static int mt7621_pci_phy_exit(struct phy *phy) { … } static const struct phy_ops mt7621_pci_phy_ops = …; static struct phy *mt7621_pcie_phy_of_xlate(struct device *dev, const struct of_phandle_args *args) { … } static const struct soc_device_attribute mt7621_pci_quirks_match[] = …; static const struct regmap_config mt7621_pci_phy_regmap_config = …; static int mt7621_pci_phy_probe(struct platform_device *pdev) { … } static const struct of_device_id mt7621_pci_phy_ids[] = …; MODULE_DEVICE_TABLE(of, mt7621_pci_phy_ids); static struct platform_driver mt7621_pci_phy_driver = …; builtin_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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