/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2010-2015 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Exynos - Power management unit definition * * Notice: * This is not a list of all Exynos Power Management Unit SFRs. * There are too many of them, not mentioning subtle differences * between SoCs. For now, put here only the used registers. */ #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H #define __LINUX_SOC_EXYNOS_REGS_PMU_H … #define S5P_CENTRAL_SEQ_CONFIGURATION … #define S5P_CENTRAL_LOWPWR_CFG … #define S5P_CENTRAL_SEQ_OPTION … #define S5P_USE_STANDBY_WFI0 … #define S5P_USE_STANDBY_WFI1 … #define S5P_USE_STANDBY_WFI2 … #define S5P_USE_STANDBY_WFI3 … #define S5P_USE_STANDBY_WFE0 … #define S5P_USE_STANDBY_WFE1 … #define S5P_USE_STANDBY_WFE2 … #define S5P_USE_STANDBY_WFE3 … #define S5P_USE_STANDBY_WFI_ALL … #define S5P_USE_DELAYED_RESET_ASSERTION … #define EXYNOS_CORE_PO_RESET(n) … #define EXYNOS_WAKEUP_FROM_LOWPWR … #define EXYNOS_SWRESET … #define S5P_WAKEUP_STAT … /* Value for EXYNOS_EINT_WAKEUP_MASK disabling all external wakeup interrupts */ #define EXYNOS_EINT_WAKEUP_MASK_DISABLED … #define EXYNOS_EINT_WAKEUP_MASK … #define S5P_WAKEUP_MASK … #define S5P_WAKEUP_MASK2 … /* MIPI_PHYn_CONTROL, valid for Exynos3250, Exynos4, Exynos5250 and Exynos5433 */ #define EXYNOS4_MIPI_PHY_CONTROL(n) … /* Phy enable bit, common for all phy registers, not only MIPI */ #define EXYNOS4_PHY_ENABLE … #define EXYNOS4_MIPI_PHY_SRESETN … #define EXYNOS4_MIPI_PHY_MRESETN … #define EXYNOS4_MIPI_PHY_RESET_MASK … #define S5P_INFORM0 … #define S5P_INFORM1 … #define S5P_INFORM5 … #define S5P_INFORM6 … #define S5P_INFORM7 … #define S5P_PMU_SPARE2 … #define S5P_PMU_SPARE3 … #define EXYNOS_IROM_DATA2 … #define S5P_ARM_CORE0_LOWPWR … #define S5P_DIS_IRQ_CORE0 … #define S5P_DIS_IRQ_CENTRAL0 … #define S5P_ARM_CORE1_LOWPWR … #define S5P_DIS_IRQ_CORE1 … #define S5P_DIS_IRQ_CENTRAL1 … #define S5P_ARM_COMMON_LOWPWR … #define S5P_L2_0_LOWPWR … #define S5P_L2_1_LOWPWR … #define S5P_CMU_ACLKSTOP_LOWPWR … #define S5P_CMU_SCLKSTOP_LOWPWR … #define S5P_CMU_RESET_LOWPWR … #define S5P_APLL_SYSCLK_LOWPWR … #define S5P_MPLL_SYSCLK_LOWPWR … #define S5P_VPLL_SYSCLK_LOWPWR … #define S5P_EPLL_SYSCLK_LOWPWR … #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR … #define S5P_CMU_RESET_GPSALIVE_LOWPWR … #define S5P_CMU_CLKSTOP_CAM_LOWPWR … #define S5P_CMU_CLKSTOP_TV_LOWPWR … #define S5P_CMU_CLKSTOP_MFC_LOWPWR … #define S5P_CMU_CLKSTOP_G3D_LOWPWR … #define S5P_CMU_CLKSTOP_LCD0_LOWPWR … #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR … #define S5P_CMU_CLKSTOP_GPS_LOWPWR … #define S5P_CMU_RESET_CAM_LOWPWR … #define S5P_CMU_RESET_TV_LOWPWR … #define S5P_CMU_RESET_MFC_LOWPWR … #define S5P_CMU_RESET_G3D_LOWPWR … #define S5P_CMU_RESET_LCD0_LOWPWR … #define S5P_CMU_RESET_MAUDIO_LOWPWR … #define S5P_CMU_RESET_GPS_LOWPWR … #define S5P_TOP_BUS_LOWPWR … #define S5P_TOP_RETENTION_LOWPWR … #define S5P_TOP_PWR_LOWPWR … #define S5P_LOGIC_RESET_LOWPWR … #define S5P_ONENAND_MEM_LOWPWR … #define S5P_G2D_ACP_MEM_LOWPWR … #define S5P_USBOTG_MEM_LOWPWR … #define S5P_HSMMC_MEM_LOWPWR … #define S5P_CSSYS_MEM_LOWPWR … #define S5P_SECSS_MEM_LOWPWR … #define S5P_PAD_RETENTION_DRAM_LOWPWR … #define S5P_PAD_RETENTION_MAUDIO_LOWPWR … #define S5P_PAD_RETENTION_GPIO_LOWPWR … #define S5P_PAD_RETENTION_UART_LOWPWR … #define S5P_PAD_RETENTION_MMCA_LOWPWR … #define S5P_PAD_RETENTION_MMCB_LOWPWR … #define S5P_PAD_RETENTION_EBIA_LOWPWR … #define S5P_PAD_RETENTION_EBIB_LOWPWR … #define S5P_PAD_RETENTION_ISOLATION_LOWPWR … #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR … #define S5P_XUSBXTI_LOWPWR … #define S5P_XXTI_LOWPWR … #define S5P_EXT_REGULATOR_LOWPWR … #define S5P_GPIO_MODE_LOWPWR … #define S5P_GPIO_MODE_MAUDIO_LOWPWR … #define S5P_CAM_LOWPWR … #define S5P_TV_LOWPWR … #define S5P_MFC_LOWPWR … #define S5P_G3D_LOWPWR … #define S5P_LCD0_LOWPWR … #define S5P_MAUDIO_LOWPWR … #define S5P_GPS_LOWPWR … #define S5P_GPS_ALIVE_LOWPWR … #define EXYNOS_ARM_CORE0_CONFIGURATION … #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) … #define EXYNOS_ARM_CORE_STATUS(_nr) … #define EXYNOS_ARM_CORE_OPTION(_nr) … #define EXYNOS_ARM_COMMON_CONFIGURATION … #define EXYNOS_COMMON_CONFIGURATION(_nr) … #define EXYNOS_COMMON_STATUS(_nr) … #define EXYNOS_COMMON_OPTION(_nr) … #define EXYNOS_ARM_L2_CONFIGURATION … #define EXYNOS_L2_CONFIGURATION(_nr) … #define EXYNOS_L2_STATUS(_nr) … #define EXYNOS_L2_OPTION(_nr) … #define EXYNOS_L2_USE_RETENTION … #define S5P_PAD_RET_MAUDIO_OPTION … #define S5P_PAD_RET_MMC2_OPTION … #define S5P_PAD_RET_GPIO_OPTION … #define S5P_PAD_RET_UART_OPTION … #define S5P_PAD_RET_MMCA_OPTION … #define S5P_PAD_RET_MMCB_OPTION … #define S5P_PAD_RET_EBIA_OPTION … #define S5P_PAD_RET_EBIB_OPTION … #define S5P_PAD_RET_SPI_OPTION … #define S5P_PS_HOLD_CONTROL … #define S5P_PS_HOLD_EN … #define S5P_PS_HOLD_OUTPUT_HIGH … #define S5P_CAM_OPTION … #define S5P_MFC_OPTION … #define S5P_G3D_OPTION … #define S5P_LCD0_OPTION … #define S5P_LCD1_OPTION … #define S5P_ISP_OPTION … #define S5P_CORE_LOCAL_PWR_EN … #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG … #define S5P_CORE_AUTOWAKEUP_EN … /* Only for S5Pv210 */ #define S5PV210_EINT_WAKEUP_MASK … /* Only for Exynos4210 */ #define S5P_CMU_CLKSTOP_LCD1_LOWPWR … #define S5P_CMU_RESET_LCD1_LOWPWR … #define S5P_MODIMIF_MEM_LOWPWR … #define S5P_PCIE_MEM_LOWPWR … #define S5P_SATA_MEM_LOWPWR … #define S5P_LCD1_LOWPWR … /* Only for Exynos4x12 */ #define S5P_ISP_ARM_LOWPWR … #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR … #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR … #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR … #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR … #define S5P_CMU_RESET_COREBLK_LOWPWR … #define S5P_MPLLUSER_SYSCLK_LOWPWR … #define S5P_CMU_CLKSTOP_ISP_LOWPWR … #define S5P_CMU_RESET_ISP_LOWPWR … #define S5P_TOP_BUS_COREBLK_LOWPWR … #define S5P_TOP_RETENTION_COREBLK_LOWPWR … #define S5P_TOP_PWR_COREBLK_LOWPWR … #define S5P_OSCCLK_GATE_LOWPWR … #define S5P_LOGIC_RESET_COREBLK_LOWPWR … #define S5P_OSCCLK_GATE_COREBLK_LOWPWR … #define S5P_HSI_MEM_LOWPWR … #define S5P_ROTATOR_MEM_LOWPWR … #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR … #define S5P_PAD_ISOLATION_COREBLK_LOWPWR … #define S5P_GPIO_MODE_COREBLK_LOWPWR … #define S5P_TOP_ASB_RESET_LOWPWR … #define S5P_TOP_ASB_ISOLATION_LOWPWR … #define S5P_ISP_LOWPWR … #define S5P_DRAM_FREQ_DOWN_LOWPWR … #define S5P_DDRPHY_DLLOFF_LOWPWR … #define S5P_CMU_SYSCLK_ISP_LOWPWR … #define S5P_CMU_SYSCLK_GPS_LOWPWR … #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR … #define S5P_ARM_L2_0_OPTION … #define S5P_ARM_L2_1_OPTION … #define S5P_ONENAND_MEM_OPTION … #define S5P_HSI_MEM_OPTION … #define S5P_G2D_ACP_MEM_OPTION … #define S5P_USBOTG_MEM_OPTION … #define S5P_HSMMC_MEM_OPTION … #define S5P_CSSYS_MEM_OPTION … #define S5P_SECSS_MEM_OPTION … #define S5P_ROTATOR_MEM_OPTION … /* Only for Exynos4412 */ #define S5P_ARM_CORE2_LOWPWR … #define S5P_DIS_IRQ_CORE2 … #define S5P_DIS_IRQ_CENTRAL2 … #define S5P_ARM_CORE3_LOWPWR … #define S5P_DIS_IRQ_CORE3 … #define S5P_DIS_IRQ_CENTRAL3 … /* Only for Exynos3XXX */ #define EXYNOS3_ARM_CORE0_SYS_PWR_REG … #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG … #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG … #define EXYNOS3_ARM_CORE1_SYS_PWR_REG … #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG … #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG … #define EXYNOS3_ISP_ARM_SYS_PWR_REG … #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG … #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG … #define EXYNOS3_ARM_COMMON_SYS_PWR_REG … #define EXYNOS3_ARM_L2_SYS_PWR_REG … #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG … #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_SYS_PWR_REG … #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG … #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG … #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG … #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG … #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG … #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG … #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG … #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG … #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG … #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG … #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG … #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG … #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG … #define EXYNOS3_TOP_BUS_SYS_PWR_REG … #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG … #define EXYNOS3_TOP_PWR_SYS_PWR_REG … #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG … #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG … #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG … #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG … #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG … #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG … #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG … #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG … #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG … #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG … #define EXYNOS3_XUSBXTI_SYS_PWR_REG … #define EXYNOS3_XXTI_SYS_PWR_REG … #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG … #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG … #define EXYNOS3_GPIO_MODE_SYS_PWR_REG … #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG … #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG … #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG … #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG … #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG … #define EXYNOS3_CAM_SYS_PWR_REG … #define EXYNOS3_MFC_SYS_PWR_REG … #define EXYNOS3_G3D_SYS_PWR_REG … #define EXYNOS3_LCD0_SYS_PWR_REG … #define EXYNOS3_ISP_SYS_PWR_REG … #define EXYNOS3_MAUDIO_SYS_PWR_REG … #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG … #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG … #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG … #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG … #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS3_ARM_CORE0_OPTION … #define EXYNOS3_ARM_CORE_OPTION(_nr) … #define EXYNOS3_ARM_COMMON_OPTION … #define EXYNOS3_ARM_L2_OPTION … #define EXYNOS3_TOP_PWR_OPTION … #define EXYNOS3_CORE_TOP_PWR_OPTION … #define EXYNOS3_XUSBXTI_DURATION … #define EXYNOS3_XXTI_DURATION … #define EXYNOS3_EXT_REGULATOR_DURATION … #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION … #define XUSBXTI_DURATION … #define XXTI_DURATION … #define EXT_REGULATOR_DURATION … #define EXT_REGULATOR_COREBLK_DURATION … /* for XXX_OPTION */ #define EXYNOS3_OPTION_USE_SC_COUNTER … #define EXYNOS3_OPTION_USE_SC_FEEDBACK … #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN … /* For Exynos5 */ #define EXYNOS5_AUTO_WDTRESET_DISABLE … #define EXYNOS5_MASK_WDTRESET_REQUEST … #define EXYNOS5_USBDRD_PHY_CONTROL … #define EXYNOS5_DPTX_PHY_CONTROL … #define EXYNOS5_USE_RETENTION … #define EXYNOS5_SYS_WDTRESET … #define EXYNOS5_ARM_CORE0_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG … #define EXYNOS5_ARM_CORE1_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG … #define EXYNOS5_FSYS_ARM_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG … #define EXYNOS5_ISP_ARM_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG … #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG … #define EXYNOS5_ARM_COMMON_SYS_PWR_REG … #define EXYNOS5_ARM_L2_SYS_PWR_REG … #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG … #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_SYS_PWR_REG … #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG … #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG … #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG … #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG … #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG … #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG … #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG … #define EXYNOS5_TOP_BUS_SYS_PWR_REG … #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG … #define EXYNOS5_TOP_PWR_SYS_PWR_REG … #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG … #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG … #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG … #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG … #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG … #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG … #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG … #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG … #define EXYNOS5_G2D_MEM_SYS_PWR_REG … #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG … #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG … #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG … #define EXYNOS5_SECSS_MEM_SYS_PWR_REG … #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG … #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG … #define EXYNOS5_INTROM_MEM_SYS_PWR_REG … #define EXYNOS5_JPEG_MEM_SYS_PWR_REG … #define EXYNOS5_HSI_MEM_SYS_PWR_REG … #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG … #define EXYNOS5_SATA_MEM_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG … #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG … #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG … #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG … #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG … #define EXYNOS5_XUSBXTI_SYS_PWR_REG … #define EXYNOS5_XXTI_SYS_PWR_REG … #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG … #define EXYNOS5_GPIO_MODE_SYS_PWR_REG … #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG … #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG … #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG … #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG … #define EXYNOS5_GSCL_SYS_PWR_REG … #define EXYNOS5_ISP_SYS_PWR_REG … #define EXYNOS5_MFC_SYS_PWR_REG … #define EXYNOS5_G3D_SYS_PWR_REG … #define EXYNOS5_DISP1_SYS_PWR_REG … #define EXYNOS5_MAU_SYS_PWR_REG … #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG … #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG … #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG … #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG … #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG … #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG … #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG … #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG … #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG … #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG … #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG … #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG … #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG … #define EXYNOS5_ARM_CORE0_OPTION … #define EXYNOS5_ARM_CORE1_OPTION … #define EXYNOS5_FSYS_ARM_OPTION … #define EXYNOS5_ISP_ARM_OPTION … #define EXYNOS5_ARM_COMMON_OPTION … #define EXYNOS5_ARM_L2_OPTION … #define EXYNOS5_TOP_PWR_OPTION … #define EXYNOS5_TOP_PWR_SYSMEM_OPTION … #define EXYNOS5_JPEG_MEM_OPTION … #define EXYNOS5_GSCL_OPTION … #define EXYNOS5_ISP_OPTION … #define EXYNOS5_MFC_OPTION … #define EXYNOS5_G3D_OPTION … #define EXYNOS5_DISP1_OPTION … #define EXYNOS5_MAU_OPTION … #define EXYNOS5_USE_SC_FEEDBACK … #define EXYNOS5_USE_SC_COUNTER … #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN … #define EXYNOS5_OPTION_USE_STANDBYWFE … #define EXYNOS5_OPTION_USE_STANDBYWFI … #define EXYNOS5_OPTION_USE_RETENTION … #define EXYNOS5420_SWRESET_KFC_SEL … /* Only for Exynos5420 */ #define EXYNOS5420_L2RSTDISABLE_VALUE … #define EXYNOS5420_LPI_MASK … #define EXYNOS5420_LPI_MASK1 … #define EXYNOS5420_UFS … #define EXYNOS5420_ATB_KFC … #define EXYNOS5420_ATB_ISP_ARM … #define EXYNOS5420_EMULATION … #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE … #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI … #define EXYNOS5420_UP_SCHEDULER … #define SPREAD_ENABLE … #define SPREAD_USE_STANDWFI … #define EXYNOS5420_KFC_CORE_RESET0 … #define EXYNOS5420_KFC_ETM_RESET0 … #define EXYNOS5420_KFC_CORE_RESET(_nr) … #define EXYNOS5420_USBDRD1_PHY_CONTROL … #define EXYNOS5420_MIPI_PHY_CONTROL(n) … #define EXYNOS5420_DPTX_PHY_CONTROL … #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_ISP_ARM_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG … #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG … #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG … #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG … #define EXYNOS5420_KFC_L2_SYS_PWR_REG … #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG … #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG … #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG … #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG … #define EXYNOS5420_DISP1_SYS_PWR_REG … #define EXYNOS5420_MAU_SYS_PWR_REG … #define EXYNOS5420_G2D_SYS_PWR_REG … #define EXYNOS5420_MSC_SYS_PWR_REG … #define EXYNOS5420_FSYS_SYS_PWR_REG … #define EXYNOS5420_FSYS2_SYS_PWR_REG … #define EXYNOS5420_PSGEN_SYS_PWR_REG … #define EXYNOS5420_PERIC_SYS_PWR_REG … #define EXYNOS5420_WCORE_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG … #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG … #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG … #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG … #define EXYNOS5420_SFR_AXI_CGDIS1 … #define EXYNOS5420_ARM_COMMON_OPTION … #define EXYNOS5420_KFC_COMMON_OPTION … #define EXYNOS5420_LOGIC_RESET_DURATION3 … #define EXYNOS5420_PAD_RET_GPIO_OPTION … #define EXYNOS5420_PAD_RET_UART_OPTION … #define EXYNOS5420_PAD_RET_MMCA_OPTION … #define EXYNOS5420_PAD_RET_MMCB_OPTION … #define EXYNOS5420_PAD_RET_MMCC_OPTION … #define EXYNOS5420_PAD_RET_HSI_OPTION … #define EXYNOS5420_PAD_RET_SPI_OPTION … #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION … #define EXYNOS_PAD_RET_DRAM_OPTION … #define EXYNOS_PAD_RET_MAUDIO_OPTION … #define EXYNOS_PAD_RET_JTAG_OPTION … #define EXYNOS_PAD_RET_EBIA_OPTION … #define EXYNOS_PAD_RET_EBIB_OPTION … #define EXYNOS5420_FSYS2_OPTION … #define EXYNOS5420_PSGEN_OPTION … #define EXYNOS5420_ARM_USE_STANDBY_WFI0 … #define EXYNOS5420_ARM_USE_STANDBY_WFI1 … #define EXYNOS5420_ARM_USE_STANDBY_WFI2 … #define EXYNOS5420_ARM_USE_STANDBY_WFI3 … #define EXYNOS5420_KFC_USE_STANDBY_WFI0 … #define EXYNOS5420_KFC_USE_STANDBY_WFI1 … #define EXYNOS5420_KFC_USE_STANDBY_WFI2 … #define EXYNOS5420_KFC_USE_STANDBY_WFI3 … #define EXYNOS5420_ARM_USE_STANDBY_WFE0 … #define EXYNOS5420_ARM_USE_STANDBY_WFE1 … #define EXYNOS5420_ARM_USE_STANDBY_WFE2 … #define EXYNOS5420_ARM_USE_STANDBY_WFE3 … #define EXYNOS5420_KFC_USE_STANDBY_WFE0 … #define EXYNOS5420_KFC_USE_STANDBY_WFE1 … #define EXYNOS5420_KFC_USE_STANDBY_WFE2 … #define EXYNOS5420_KFC_USE_STANDBY_WFE3 … #define DUR_WAIT_RESET … #define EXYNOS5420_USE_STANDBY_WFI_ALL … /* For Exynos5433 */ #define EXYNOS5433_EINT_WAKEUP_MASK … #define EXYNOS5433_USBHOST30_PHY_CONTROL … #define EXYNOS5433_PAD_RETENTION_AUD_OPTION … #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION … #define EXYNOS5433_PAD_RETENTION_TOP_OPTION … #define EXYNOS5433_PAD_RETENTION_UART_OPTION … #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION … #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION … #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION … #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION … #define EXYNOS5433_PAD_RETENTION_SPI_OPTION … #define EXYNOS5433_PAD_RETENTION_MIF_OPTION … #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION … #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION … #define EXYNOS5433_PAD_RETENTION_UFS_OPTION … #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION … /* For Tensor GS101 */ #define GS101_SYSIP_DAT0 … #define GS101_SYSTEM_CONFIGURATION … #define GS101_PHY_CTRL_USB20 … #define GS101_PHY_CTRL_USBDP … #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
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