/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _I915_REG_H_ #define _I915_REG_H_ #include "i915_reg_defs.h" #include "display/intel_display_reg_defs.h" /** * DOC: The i915 register macro definition style guide * * Follow the style described here for new macros, and while changing existing * macros. Do **not** mass change existing definitions just to update the style. * * File Layout * ~~~~~~~~~~~ * * Keep helper macros near the top. For example, _PIPE() and friends. * * Prefix macros that generally should not be used outside of this file with * underscore '_'. For example, _PIPE() and friends, single instances of * registers that are defined solely for the use by function-like macros. * * Avoid using the underscore prefixed macros outside of this file. There are * exceptions, but keep them to a minimum. * * There are two basic types of register definitions: Single registers and * register groups. Register groups are registers which have two or more * instances, for example one per pipe, port, transcoder, etc. Register groups * should be defined using function-like macros. * * For single registers, define the register offset first, followed by register * contents. * * For register groups, define the register instance offsets first, prefixed * with underscore, followed by a function-like macro choosing the right * instance based on the parameter, followed by register contents. * * Define the register contents (i.e. bit and bit field macros) from most * significant to least significant bit. Indent the register content macros * using two extra spaces between ``#define`` and the macro name. * * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents * using ``REG_FIELD_PREP(mask, value)``. This will define the values already * shifted in place, so they can be directly OR'd together. For convenience, * function-like macros may be used to define bit fields, but do note that the * macros may be needed to read as well as write the register contents. * * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. * * Group the register and its contents together without blank lines, separate * from other registers and their contents with one blank line. * * Indent macro values from macro names using TABs. Align values vertically. Use * braces in macro values as needed to avoid unintended precedence after macro * substitution. Use spaces in macro values according to kernel coding * style. Use lower case in hexadecimal values. * * Naming * ~~~~~~ * * Try to name registers according to the specs. If the register name changes in * the specs from platform to another, stick to the original name. * * Try to re-use existing register macro definitions. Only add new macros for * new register offsets, or when the register contents have changed enough to * warrant a full redefinition. * * When a register macro changes for a new platform, prefix the new macro using * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The * prefix signifies the start platform/generation using the register. * * When a bit (field) macro changes or gets added for a new platform, while * retaining the existing register macro, add a platform acronym or generation * suffix to the name. For example, ``_SKL`` or ``_GEN8``. * * Examples * ~~~~~~~~ * * (Note that the values in the example are indented using spaces instead of * TABs to avoid misalignment in generated documentation. Use TABs in the * definitions.):: * * #define _FOO_A 0xf000 * #define _FOO_B 0xf001 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) * #define FOO_ENABLE REG_BIT(31) * #define FOO_MODE_MASK REG_GENMASK(19, 16) * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) * * #define BAR _MMIO(0xb000) * #define GEN8_BAR _MMIO(0xb888) */ #define GU_CNTL_PROTECTED … #define DEPRESENT … #define GU_CNTL … #define LMEM_INIT … #define DRIVERFLR … #define GU_DEBUG … #define DRIVERFLR_STATUS … #define GEN6_STOLEN_RESERVED … #define GEN6_STOLEN_RESERVED_ADDR_MASK … #define GEN7_STOLEN_RESERVED_ADDR_MASK … #define GEN6_STOLEN_RESERVED_SIZE_MASK … #define GEN6_STOLEN_RESERVED_1M … #define GEN6_STOLEN_RESERVED_512K … #define GEN6_STOLEN_RESERVED_256K … #define GEN6_STOLEN_RESERVED_128K … #define GEN7_STOLEN_RESERVED_SIZE_MASK … #define GEN7_STOLEN_RESERVED_1M … #define GEN7_STOLEN_RESERVED_256K … #define GEN8_STOLEN_RESERVED_SIZE_MASK … #define GEN8_STOLEN_RESERVED_1M … #define GEN8_STOLEN_RESERVED_2M … #define GEN8_STOLEN_RESERVED_4M … #define GEN8_STOLEN_RESERVED_8M … #define GEN6_STOLEN_RESERVED_ENABLE … #define GEN11_STOLEN_RESERVED_ADDR_MASK … #define _VGA_MSR_WRITE … #define _GEN7_PIPEA_DE_LOAD_SL … #define _GEN7_PIPEB_DE_LOAD_SL … #define GEN7_PIPE_DE_LOAD_SL(pipe) … /* * Reset registers */ #define DEBUG_RESET_I830 … #define DEBUG_RESET_FULL … #define DEBUG_RESET_RENDER … #define DEBUG_RESET_DISPLAY … /* * IOSF sideband */ #define VLV_IOSF_DOORBELL_REQ … #define IOSF_DEVFN_SHIFT … #define IOSF_OPCODE_SHIFT … #define IOSF_PORT_SHIFT … #define IOSF_BYTE_ENABLES_SHIFT … #define IOSF_BAR_SHIFT … #define IOSF_SB_BUSY … #define IOSF_PORT_BUNIT … #define IOSF_PORT_PUNIT … #define IOSF_PORT_NC … #define IOSF_PORT_DPIO … #define IOSF_PORT_GPIO_NC … #define IOSF_PORT_CCK … #define IOSF_PORT_DPIO_2 … #define IOSF_PORT_FLISDSI … #define IOSF_PORT_GPIO_SC … #define IOSF_PORT_GPIO_SUS … #define IOSF_PORT_CCU … #define CHV_IOSF_PORT_GPIO_N … #define CHV_IOSF_PORT_GPIO_SE … #define CHV_IOSF_PORT_GPIO_E … #define CHV_IOSF_PORT_GPIO_SW … #define VLV_IOSF_DATA … #define VLV_IOSF_ADDR … /* DPIO registers */ #define DPIO_DEVFN … #define DPIO_CTL … #define DPIO_MODSEL1 … #define DPIO_MODSEL0 … #define DPIO_SFR_BYPASS … #define DPIO_CMNRST … #define BXT_P_CR_GT_DISP_PWRON … #define MIPIO_RST_CTRL … #define _BXT_PHY_CTL_DDI_A … #define _BXT_PHY_CTL_DDI_B … #define _BXT_PHY_CTL_DDI_C … #define BXT_PHY_CMNLANE_POWERDOWN_ACK … #define BXT_PHY_LANE_POWERDOWN_ACK … #define BXT_PHY_LANE_ENABLED … #define BXT_PHY_CTL(port) … #define _PHY_CTL_FAMILY_DDI … #define _PHY_CTL_FAMILY_EDP … #define _PHY_CTL_FAMILY_DDI_C … #define COMMON_RESET_DIS … #define BXT_PHY_CTL_FAMILY(phy) … /* UAIMI scratch pad register 1 */ #define UAIMI_SPR1 … /* SKL VccIO mask */ #define SKL_VCCIO_MASK … /* SKL balance leg register */ #define DISPIO_CR_TX_BMU_CR0 … /* I_boost values */ #define BALANCE_LEG_SHIFT(port) … #define BALANCE_LEG_MASK(port) … /* Balance leg disable bits */ #define BALANCE_LEG_DISABLE_SHIFT … #define BALANCE_LEG_DISABLE(port) … /* * Fence registers * [0-7] @ 0x2000 gen2,gen3 * [8-15] @ 0x3000 945,g33,pnv * * [0-15] @ 0x3000 gen4,gen5 * * [0-15] @ 0x100000 gen6,vlv,chv * [0-31] @ 0x100000 gen7+ */ #define FENCE_REG(i) … #define I830_FENCE_START_MASK … #define I830_FENCE_TILING_Y_SHIFT … #define I830_FENCE_SIZE_BITS(size) … #define I830_FENCE_PITCH_SHIFT … #define I830_FENCE_REG_VALID … #define I915_FENCE_MAX_PITCH_VAL … #define I830_FENCE_MAX_PITCH_VAL … #define I830_FENCE_MAX_SIZE_VAL … #define I915_FENCE_START_MASK … #define I915_FENCE_SIZE_BITS(size) … #define FENCE_REG_965_LO(i) … #define FENCE_REG_965_HI(i) … #define I965_FENCE_PITCH_SHIFT … #define I965_FENCE_TILING_Y_SHIFT … #define I965_FENCE_REG_VALID … #define I965_FENCE_MAX_PITCH_VAL … #define FENCE_REG_GEN6_LO(i) … #define FENCE_REG_GEN6_HI(i) … #define GEN6_FENCE_PITCH_SHIFT … #define GEN7_FENCE_MAX_PITCH_VAL … /* control register for cpu gtt access */ #define TILECTL … #define TILECTL_SWZCTL … #define TILECTL_TLBPF … #define TILECTL_TLB_PREFETCH_DIS … #define TILECTL_BACKSNOOP_DIS … /* * Instruction and interrupt control regs */ #define PGTBL_CTL … #define PGTBL_ADDRESS_LO_MASK … #define PGTBL_ADDRESS_HI_MASK … #define PGTBL_ER … #define PRB0_BASE … #define PRB1_BASE … #define PRB2_BASE … #define SRB0_BASE … #define SRB1_BASE … #define SRB2_BASE … #define SRB3_BASE … #define RENDER_RING_BASE … #define BSD_RING_BASE … #define GEN6_BSD_RING_BASE … #define GEN8_BSD2_RING_BASE … #define GEN11_BSD_RING_BASE … #define GEN11_BSD2_RING_BASE … #define GEN11_BSD3_RING_BASE … #define GEN11_BSD4_RING_BASE … #define XEHP_BSD5_RING_BASE … #define XEHP_BSD6_RING_BASE … #define XEHP_BSD7_RING_BASE … #define XEHP_BSD8_RING_BASE … #define VEBOX_RING_BASE … #define GEN11_VEBOX_RING_BASE … #define GEN11_VEBOX2_RING_BASE … #define XEHP_VEBOX3_RING_BASE … #define XEHP_VEBOX4_RING_BASE … #define MTL_GSC_RING_BASE … #define GEN12_COMPUTE0_RING_BASE … #define GEN12_COMPUTE1_RING_BASE … #define GEN12_COMPUTE2_RING_BASE … #define GEN12_COMPUTE3_RING_BASE … #define BLT_RING_BASE … #define XEHPC_BCS1_RING_BASE … #define XEHPC_BCS2_RING_BASE … #define XEHPC_BCS3_RING_BASE … #define XEHPC_BCS4_RING_BASE … #define XEHPC_BCS5_RING_BASE … #define XEHPC_BCS6_RING_BASE … #define XEHPC_BCS7_RING_BASE … #define XEHPC_BCS8_RING_BASE … #define DG1_GSC_HECI1_BASE … #define DG1_GSC_HECI2_BASE … #define DG2_GSC_HECI1_BASE … #define DG2_GSC_HECI2_BASE … #define MTL_GSC_HECI1_BASE … #define MTL_GSC_HECI2_BASE … #define HECI_H_CSR(base) … #define HECI_H_CSR_IE … #define HECI_H_CSR_IS … #define HECI_H_CSR_IG … #define HECI_H_CSR_RDY … #define HECI_H_CSR_RST … #define HECI_H_GS1(base) … #define HECI_H_GS1_ER_PREP … /* * The FWSTS register values are FW defined and can be different between * HECI1 and HECI2 */ #define HECI_FWSTS1 … #define HECI1_FWSTS1_CURRENT_STATE … #define HECI1_FWSTS1_CURRENT_STATE_RESET … #define HECI1_FWSTS1_PROXY_STATE_NORMAL … #define HECI1_FWSTS1_INIT_COMPLETE … #define HECI_FWSTS2 … #define HECI_FWSTS3 … #define HECI_FWSTS4 … #define HECI_FWSTS5 … #define HECI1_FWSTS5_HUC_AUTH_DONE … #define HECI_FWSTS6 … /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */ #define HECI_FWSTS(base, x) … #define HSW_GTT_CACHE_EN … #define GTT_CACHE_EN_ALL … #define GEN7_WR_WATERMARK … #define GEN7_GFX_PRIO_CTRL … #define ARB_MODE … #define ARB_MODE_SWIZZLE_SNB … #define ARB_MODE_SWIZZLE_IVB … #define GEN7_GFX_PEND_TLB0 … #define GEN7_GFX_PEND_TLB1 … /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ #define GEN7_LRA_LIMITS(i) … #define GEN7_LRA_LIMITS_REG_NUM … #define GEN7_MEDIA_MAX_REQ_COUNT … #define GEN7_GFX_MAX_REQ_COUNT … #define GEN7_ERR_INT … #define ERR_INT_POISON … #define ERR_INT_MMIO_UNCLAIMED … #define ERR_INT_PIPE_CRC_DONE_C … #define ERR_INT_FIFO_UNDERRUN_C … #define ERR_INT_PIPE_CRC_DONE_B … #define ERR_INT_FIFO_UNDERRUN_B … #define ERR_INT_PIPE_CRC_DONE_A … #define ERR_INT_PIPE_CRC_DONE(pipe) … #define ERR_INT_FIFO_UNDERRUN_A … #define ERR_INT_FIFO_UNDERRUN(pipe) … #define FPGA_DBG … #define FPGA_DBG_RM_NOCLAIM … #define CLAIM_ER … #define CLAIM_ER_CLR … #define CLAIM_ER_OVERFLOW … #define CLAIM_ER_CTR_MASK … #define DERRMR … /* Note that HBLANK events are reserved on bdw+ */ #define DERRMR_PIPEA_SCANLINE … #define DERRMR_PIPEA_PRI_FLIP_DONE … #define DERRMR_PIPEA_SPR_FLIP_DONE … #define DERRMR_PIPEA_VBLANK … #define DERRMR_PIPEA_HBLANK … #define DERRMR_PIPEB_SCANLINE … #define DERRMR_PIPEB_PRI_FLIP_DONE … #define DERRMR_PIPEB_SPR_FLIP_DONE … #define DERRMR_PIPEB_VBLANK … #define DERRMR_PIPEB_HBLANK … /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ #define DERRMR_PIPEC_SCANLINE … #define DERRMR_PIPEC_PRI_FLIP_DONE … #define DERRMR_PIPEC_SPR_FLIP_DONE … #define DERRMR_PIPEC_VBLANK … #define DERRMR_PIPEC_HBLANK … #define VLV_GU_CTL0 … #define VLV_GU_CTL1 … #define SCPD0 … #define SCPD_FBC_IGNORE_3D … #define CSTATE_RENDER_CLOCK_GATE_DISABLE … #define GEN2_IER … #define GEN2_IIR … #define GEN2_IMR … #define GEN2_ISR … #define VLV_GUNIT_CLOCK_GATE … #define GINT_DIS … #define GCFG_DIS … #define VLV_GUNIT_CLOCK_GATE2 … #define VLV_IIR_RW … #define VLV_IER … #define VLV_IIR … #define VLV_IMR … #define VLV_ISR … #define VLV_PCBR … #define VLV_PCBR_ADDR_SHIFT … #define DISPLAY_PLANE_FLIP_PENDING(plane) … #define EIR … #define EMR … #define ESR … #define GM45_ERROR_PAGE_TABLE … #define GM45_ERROR_MEM_PRIV … #define I915_ERROR_PAGE_TABLE … #define GM45_ERROR_CP_PRIV … #define I915_ERROR_MEMORY_REFRESH … #define I915_ERROR_INSTRUCTION … #define INSTPM … #define INSTPM_SELF_EN … #define INSTPM_AGPBUSY_INT_EN … #define INSTPM_FORCE_ORDERING … #define INSTPM_TLB_INVALIDATE … #define INSTPM_SYNC_FLUSH … #define MEM_MODE … #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE … #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE … #define MEM_DISPLAY_TRICKLE_FEED_DISABLE … #define FW_BLC … #define FW_BLC2 … #define FW_BLC_SELF … #define FW_BLC_SELF_EN_MASK … #define FW_BLC_SELF_FIFO_MASK … #define FW_BLC_SELF_EN … #define MM_BURST_LENGTH … #define MM_FIFO_WATERMARK … #define LM_BURST_LENGTH … #define LM_FIFO_WATERMARK … #define MI_ARB_STATE … #define _MBUS_ABOX0_CTL … #define _MBUS_ABOX1_CTL … #define _MBUS_ABOX2_CTL … #define MBUS_ABOX_CTL(x) … #define MBUS_ABOX_BW_CREDIT_MASK … #define MBUS_ABOX_BW_CREDIT(x) … #define MBUS_ABOX_B_CREDIT_MASK … #define MBUS_ABOX_B_CREDIT(x) … #define MBUS_ABOX_BT_CREDIT_POOL2_MASK … #define MBUS_ABOX_BT_CREDIT_POOL2(x) … #define MBUS_ABOX_BT_CREDIT_POOL1_MASK … #define MBUS_ABOX_BT_CREDIT_POOL1(x) … /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ #define MI_ARB_RENDER_TLB_LOW_PRIORITY … /* Isoch request wait on GTT enable (Display A/B/C streams). * Make isoch requests stall on the TLB update. May cause * display underruns (test mode only) */ #define MI_ARB_ISOCH_WAIT_GTT … /* Block grant count for isoch requests when block count is * set to a finite value. */ #define MI_ARB_BLOCK_GRANT_MASK … #define MI_ARB_BLOCK_GRANT_8 … #define MI_ARB_BLOCK_GRANT_4 … #define MI_ARB_BLOCK_GRANT_2 … #define MI_ARB_BLOCK_GRANT_0 … /* Enable render writes to complete in C2/C3/C4 power states. * If this isn't enabled, render writes are prevented in low * power states. That seems bad to me. */ #define MI_ARB_C3_LP_WRITE_ENABLE … /* This acknowledges an async flip immediately instead * of waiting for 2TLB fetches. */ #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE … /* Enables non-sequential data reads through arbiter */ #define MI_ARB_DUAL_DATA_PHASE_DISABLE … /* Disable FSB snooping of cacheable write cycles from binner/render * command stream */ #define MI_ARB_CACHE_SNOOP_DISABLE … /* Arbiter time slice for non-isoch streams */ #define MI_ARB_TIME_SLICE_MASK … #define MI_ARB_TIME_SLICE_1 … #define MI_ARB_TIME_SLICE_2 … #define MI_ARB_TIME_SLICE_4 … #define MI_ARB_TIME_SLICE_6 … #define MI_ARB_TIME_SLICE_8 … #define MI_ARB_TIME_SLICE_10 … #define MI_ARB_TIME_SLICE_14 … #define MI_ARB_TIME_SLICE_16 … /* Low priority grace period page size */ #define MI_ARB_LOW_PRIORITY_GRACE_4KB … #define MI_ARB_LOW_PRIORITY_GRACE_8KB … /* Disable display A/B trickle feed */ #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE … /* Set display plane priority */ #define MI_ARB_DISPLAY_PRIORITY_A_B … #define MI_ARB_DISPLAY_PRIORITY_B_A … #define MI_STATE … #define MI_AGPBUSY_INT_EN … #define MI_AGPBUSY_830_MODE … /* On modern GEN architectures interrupt control consists of two sets * of registers. The first set pertains to the ring generating the * interrupt. The second control is for the functional block generating the * interrupt. These are PM, GT, DE, etc. * * Luckily *knocks on wood* all the ring interrupt bits match up with the * GT interrupt bits, so we don't need to duplicate the defines. * * These defines should cover us well from SNB->HSW with minor exceptions * it can also work on ILK. */ #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT … #define GT_BLT_CS_ERROR_INTERRUPT … #define GT_BLT_USER_INTERRUPT … #define GT_BSD_CS_ERROR_INTERRUPT … #define GT_BSD_USER_INTERRUPT … #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 … #define GT_WAIT_SEMAPHORE_INTERRUPT … #define GT_CONTEXT_SWITCH_INTERRUPT … #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT … #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT … #define GT_CS_MASTER_ERROR_INTERRUPT … #define GT_RENDER_SYNC_STATUS_INTERRUPT … #define GT_RENDER_DEBUG_INTERRUPT … #define GT_RENDER_USER_INTERRUPT … #define PM_VEBOX_CS_ERROR_INTERRUPT … #define PM_VEBOX_USER_INTERRUPT … #define GT_PARITY_ERROR(dev_priv) … /* These are all the "old" interrupts */ #define ILK_BSD_USER_INTERRUPT … #define I915_PM_INTERRUPT … #define I915_ISP_INTERRUPT … #define I915_LPE_PIPE_B_INTERRUPT … #define I915_LPE_PIPE_A_INTERRUPT … #define I915_MIPIC_INTERRUPT … #define I915_MIPIA_INTERRUPT … #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT … #define I915_DISPLAY_PORT_INTERRUPT … #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT … #define I915_MASTER_ERROR_INTERRUPT … #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT … #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT … #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT … #define I915_HWB_OOM_INTERRUPT … #define I915_LPE_PIPE_C_INTERRUPT … #define I915_SYNC_STATUS_INTERRUPT … #define I915_MISC_INTERRUPT … #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT … #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT … #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT … #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT … #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT … #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT … #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT … #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT … #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT … #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT … #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT … #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT … #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT … #define I915_DEBUG_INTERRUPT … #define I915_WINVALID_INTERRUPT … #define I915_USER_INTERRUPT … #define I915_ASLE_INTERRUPT … #define I915_BSD_USER_INTERRUPT … #define GEN6_BSD_RNCID … #define GEN7_FF_THREAD_MODE … #define GEN7_FF_SCHED_MASK … #define GEN8_FF_DS_REF_CNT_FFME … #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE … #define GEN7_FF_TS_SCHED_HS1 … #define GEN7_FF_TS_SCHED_HS0 … #define GEN7_FF_TS_SCHED_LOAD_BALANCE … #define GEN7_FF_TS_SCHED_HW … #define GEN7_FF_VS_REF_CNT_FFME … #define GEN7_FF_VS_SCHED_HS1 … #define GEN7_FF_VS_SCHED_HS0 … #define GEN7_FF_VS_SCHED_LOAD_BALANCE … #define GEN7_FF_VS_SCHED_HW … #define GEN7_FF_DS_SCHED_HS1 … #define GEN7_FF_DS_SCHED_HS0 … #define GEN7_FF_DS_SCHED_LOAD_BALANCE … #define GEN7_FF_DS_SCHED_HW … #define ILK_DISPLAY_CHICKEN1 … #define ILK_FBCQ_DIS … #define ILK_PABSTRETCH_DIS … #define ILK_SABSTRETCH_DIS … #define IVB_PRI_STRETCH_MAX_MASK … #define IVB_PRI_STRETCH_MAX_X8 … #define IVB_PRI_STRETCH_MAX_X4 … #define IVB_PRI_STRETCH_MAX_X2 … #define IVB_PRI_STRETCH_MAX_X1 … #define IVB_SPR_STRETCH_MAX_MASK … #define IVB_SPR_STRETCH_MAX_X8 … #define IVB_SPR_STRETCH_MAX_X4 … #define IVB_SPR_STRETCH_MAX_X2 … #define IVB_SPR_STRETCH_MAX_X1 … #define IPS_CTL … #define IPS_ENABLE … #define IPS_FALSE_COLOR … /* * Clock control & power management */ #define _DPLL_A … #define _DPLL_B … #define _CHV_DPLL_C … #define DPLL(dev_priv, pipe) … #define VGA0 … #define VGA1 … #define VGA_PD … #define VGA0_PD_P2_DIV_4 … #define VGA0_PD_P1_DIV_2 … #define VGA0_PD_P1_SHIFT … #define VGA0_PD_P1_MASK … #define VGA1_PD_P2_DIV_4 … #define VGA1_PD_P1_DIV_2 … #define VGA1_PD_P1_SHIFT … #define VGA1_PD_P1_MASK … #define DPLL_VCO_ENABLE … #define DPLL_SDVO_HIGH_SPEED … #define DPLL_DVO_2X_MODE … #define DPLL_EXT_BUFFER_ENABLE_VLV … #define DPLL_SYNCLOCK_ENABLE … #define DPLL_REF_CLK_ENABLE_VLV … #define DPLL_VGA_MODE_DIS … #define DPLLB_MODE_DAC_SERIAL … #define DPLLB_MODE_LVDS … #define DPLL_MODE_MASK … #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 … #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 … #define DPLLB_LVDS_P2_CLOCK_DIV_14 … #define DPLLB_LVDS_P2_CLOCK_DIV_7 … #define DPLL_P2_CLOCK_DIV_MASK … #define DPLL_FPA01_P1_POST_DIV_MASK … #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW … #define DPLL_LOCK_VLV … #define DPLL_INTEGRATED_CRI_CLK_VLV … #define DPLL_INTEGRATED_REF_CLK_VLV … #define DPLL_SSC_REF_CLK_CHV … #define DPLL_PORTC_READY_MASK … #define DPLL_PORTB_READY_MASK … #define DPLL_FPA01_P1_POST_DIV_MASK_I830 … /* Additional CHV pll/phy registers */ #define DPIO_PHY_STATUS … #define DPLL_PORTD_READY_MASK … #define DISPLAY_PHY_CONTROL … #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) … #define PHY_LDO_DELAY_0NS … #define PHY_LDO_DELAY_200NS … #define PHY_LDO_DELAY_600NS … #define PHY_LDO_SEQ_DELAY(delay, phy) … #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) … #define PHY_CH_SU_PSR … #define PHY_CH_DEEP_PSR … #define PHY_CH_POWER_MODE(mode, phy, ch) … #define PHY_COM_LANE_RESET_DEASSERT(phy) … #define DISPLAY_PHY_STATUS … #define PHY_POWERGOOD(phy) … #define PHY_STATUS_CMN_LDO(phy, ch) … #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) … /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS … #define DPLL_FPA01_P1_POST_DIV_SHIFT … #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW … /* i830, required in DVO non-gang */ #define PLL_P2_DIVIDE_BY_4 … #define PLL_P1_DIVIDE_BY_TWO … #define PLL_REF_INPUT_DREFCLK … #define PLL_REF_INPUT_TVCLKINA … #define PLL_REF_INPUT_TVCLKINBC … #define PLLB_REF_INPUT_SPREADSPECTRUMIN … #define PLL_REF_INPUT_MASK … #define PLL_LOAD_PULSE_PHASE_SHIFT … /* Ironlake */ #define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT … #define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK … #define PLL_REF_SDVO_HDMI_MULTIPLIER(x) … #define DPLL_FPA1_P1_POST_DIV_SHIFT … #define DPLL_FPA1_P1_POST_DIV_MASK … /* * Parallel to Serial Load Pulse phase selection. * Selects the phase for the 10X DPLL clock for the PCIe * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 */ #define PLL_LOAD_PULSE_PHASE_MASK … #define DISPLAY_RATE_SELECT_FPA1 … /* * SDVO multiplier for 945G/GM. Not used on 965. */ #define SDVO_MULTIPLIER_MASK … #define SDVO_MULTIPLIER_SHIFT_HIRES … #define SDVO_MULTIPLIER_SHIFT_VGA … #define _DPLL_A_MD … #define _DPLL_B_MD … #define _CHV_DPLL_C_MD … #define DPLL_MD(dev_priv, pipe) … /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ #define DPLL_MD_UDI_DIVIDER_MASK … #define DPLL_MD_UDI_DIVIDER_SHIFT … /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ #define DPLL_MD_VGA_UDI_DIVIDER_MASK … #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT … /* * SDVO/UDI pixel multiplier. * * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus * clock rate is 10 times the DPLL clock. At low resolution/refresh rate * modes, the bus rate would be below the limits, so SDVO allows for stuffing * dummy bytes in the datastream at an increased clock rate, with both sides of * the link knowing how many bytes are fill. * * So, for a mode with a dotclock of 65Mhz, we would want to double the clock * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be * set to 130Mhz, and the SDVO multiplier set to 2x in this register and * through an SDVO command. * * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. */ #define DPLL_MD_UDI_MULTIPLIER_MASK … #define DPLL_MD_UDI_MULTIPLIER_SHIFT … /* * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK … #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT … #define RAWCLK_FREQ_VLV … #define _FPA0 … #define _FPA1 … #define _FPB0 … #define _FPB1 … #define FP0(pipe) … #define FP1(pipe) … #define FP_N_DIV_MASK … #define FP_N_PINEVIEW_DIV_MASK … #define FP_N_DIV_SHIFT … #define FP_M1_DIV_MASK … #define FP_M1_DIV_SHIFT … #define FP_M2_DIV_MASK … #define FP_M2_PINEVIEW_DIV_MASK … #define FP_M2_DIV_SHIFT … #define DPLL_TEST … #define DPLLB_TEST_SDVO_DIV_1 … #define DPLLB_TEST_SDVO_DIV_2 … #define DPLLB_TEST_SDVO_DIV_4 … #define DPLLB_TEST_SDVO_DIV_MASK … #define DPLLB_TEST_N_BYPASS … #define DPLLB_TEST_M_BYPASS … #define DPLLB_INPUT_BUFFER_ENABLE … #define DPLLA_TEST_N_BYPASS … #define DPLLA_TEST_M_BYPASS … #define DPLLA_INPUT_BUFFER_ENABLE … #define D_STATE … #define DSTATE_GFX_RESET_I830 … #define DSTATE_PLL_D3_OFF … #define DSTATE_GFX_CLOCK_GATING … #define DSTATE_DOT_CLOCK_GATING … #define DSPCLK_GATE_D(__i915) … #define DPUNIT_B_CLOCK_GATE_DISABLE … #define VSUNIT_CLOCK_GATE_DISABLE … #define VRHUNIT_CLOCK_GATE_DISABLE … #define VRDUNIT_CLOCK_GATE_DISABLE … #define AUDUNIT_CLOCK_GATE_DISABLE … #define DPUNIT_A_CLOCK_GATE_DISABLE … #define DPCUNIT_CLOCK_GATE_DISABLE … #define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE … #define TVRUNIT_CLOCK_GATE_DISABLE … #define TVCUNIT_CLOCK_GATE_DISABLE … #define TVFUNIT_CLOCK_GATE_DISABLE … #define TVEUNIT_CLOCK_GATE_DISABLE … #define DVSUNIT_CLOCK_GATE_DISABLE … #define DSSUNIT_CLOCK_GATE_DISABLE … #define DDBUNIT_CLOCK_GATE_DISABLE … #define DPRUNIT_CLOCK_GATE_DISABLE … #define DPFUNIT_CLOCK_GATE_DISABLE … #define DPBMUNIT_CLOCK_GATE_DISABLE … #define DPLSUNIT_CLOCK_GATE_DISABLE … #define DPLUNIT_CLOCK_GATE_DISABLE … #define DPOUNIT_CLOCK_GATE_DISABLE … #define DPBUNIT_CLOCK_GATE_DISABLE … #define DCUNIT_CLOCK_GATE_DISABLE … #define DPUNIT_CLOCK_GATE_DISABLE … #define VRUNIT_CLOCK_GATE_DISABLE … #define OVHUNIT_CLOCK_GATE_DISABLE … #define DPIOUNIT_CLOCK_GATE_DISABLE … #define OVFUNIT_CLOCK_GATE_DISABLE … #define OVBUNIT_CLOCK_GATE_DISABLE … /* * This bit must be set on the 830 to prevent hangs when turning off the * overlay scaler. */ #define OVRUNIT_CLOCK_GATE_DISABLE … #define OVCUNIT_CLOCK_GATE_DISABLE … #define OVUUNIT_CLOCK_GATE_DISABLE … #define ZVUNIT_CLOCK_GATE_DISABLE … #define OVLUNIT_CLOCK_GATE_DISABLE … #define RENCLK_GATE_D1 … #define BLITTER_CLOCK_GATE_DISABLE … #define MPEG_CLOCK_GATE_DISABLE … #define PC_FE_CLOCK_GATE_DISABLE … #define PC_BE_CLOCK_GATE_DISABLE … #define WINDOWER_CLOCK_GATE_DISABLE … #define INTERPOLATOR_CLOCK_GATE_DISABLE … #define COLOR_CALCULATOR_CLOCK_GATE_DISABLE … #define MOTION_COMP_CLOCK_GATE_DISABLE … #define MAG_CLOCK_GATE_DISABLE … /* This bit must be unset on 855,865 */ #define MECI_CLOCK_GATE_DISABLE … #define DCMP_CLOCK_GATE_DISABLE … #define MEC_CLOCK_GATE_DISABLE … #define MECO_CLOCK_GATE_DISABLE … /* This bit must be set on 855,865. */ #define SV_CLOCK_GATE_DISABLE … #define I915_MPEG_CLOCK_GATE_DISABLE … #define I915_VLD_IP_PR_CLOCK_GATE_DISABLE … #define I915_MOTION_COMP_CLOCK_GATE_DISABLE … #define I915_BD_BF_CLOCK_GATE_DISABLE … #define I915_SF_SE_CLOCK_GATE_DISABLE … #define I915_WM_CLOCK_GATE_DISABLE … #define I915_IZ_CLOCK_GATE_DISABLE … #define I915_PI_CLOCK_GATE_DISABLE … #define I915_DI_CLOCK_GATE_DISABLE … #define I915_SH_SV_CLOCK_GATE_DISABLE … #define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE … #define I915_SC_CLOCK_GATE_DISABLE … #define I915_FL_CLOCK_GATE_DISABLE … #define I915_DM_CLOCK_GATE_DISABLE … #define I915_PS_CLOCK_GATE_DISABLE … #define I915_CC_CLOCK_GATE_DISABLE … #define I915_BY_CLOCK_GATE_DISABLE … #define I965_RCZ_CLOCK_GATE_DISABLE … /* This bit must always be set on 965G/965GM */ #define I965_RCC_CLOCK_GATE_DISABLE … #define I965_RCPB_CLOCK_GATE_DISABLE … #define I965_DAP_CLOCK_GATE_DISABLE … #define I965_ROC_CLOCK_GATE_DISABLE … #define I965_GW_CLOCK_GATE_DISABLE … #define I965_TD_CLOCK_GATE_DISABLE … /* This bit must always be set on 965G */ #define I965_ISC_CLOCK_GATE_DISABLE … #define I965_IC_CLOCK_GATE_DISABLE … #define I965_EU_CLOCK_GATE_DISABLE … #define I965_IF_CLOCK_GATE_DISABLE … #define I965_TC_CLOCK_GATE_DISABLE … #define I965_SO_CLOCK_GATE_DISABLE … #define I965_FBC_CLOCK_GATE_DISABLE … #define I965_MARI_CLOCK_GATE_DISABLE … #define I965_MASF_CLOCK_GATE_DISABLE … #define I965_MAWB_CLOCK_GATE_DISABLE … #define I965_EM_CLOCK_GATE_DISABLE … #define I965_UC_CLOCK_GATE_DISABLE … #define I965_SI_CLOCK_GATE_DISABLE … #define I965_MT_CLOCK_GATE_DISABLE … #define I965_PL_CLOCK_GATE_DISABLE … #define I965_DG_CLOCK_GATE_DISABLE … #define I965_QC_CLOCK_GATE_DISABLE … #define I965_FT_CLOCK_GATE_DISABLE … #define I965_DM_CLOCK_GATE_DISABLE … #define RENCLK_GATE_D2 … #define VF_UNIT_CLOCK_GATE_DISABLE … #define GS_UNIT_CLOCK_GATE_DISABLE … #define CL_UNIT_CLOCK_GATE_DISABLE … #define VDECCLK_GATE_D … #define VCP_UNIT_CLOCK_GATE_DISABLE … #define RAMCLK_GATE_D … #define DEUC … #define FW_BLC_SELF_VLV … #define FW_CSPWRDWNEN … #define MI_ARB_VLV … #define CZCLK_CDCLK_FREQ_RATIO … #define CDCLK_FREQ_SHIFT … #define CDCLK_FREQ_MASK … #define CZCLK_FREQ_MASK … #define GCI_CONTROL … #define PFI_CREDIT_63 … #define PFI_CREDIT_31 … #define PFI_CREDIT(x) … #define PFI_CREDIT_RESEND … #define VGA_FAST_MODE_DISABLE … #define GMBUSFREQ_VLV … #define PEG_BAND_GAP_DATA … #define BXT_RP_STATE_CAP … #define GEN9_RP_STATE_LIMITS … #define MTL_RP_STATE_CAP … #define MTL_MEDIAP_STATE_CAP … #define MTL_RP0_CAP_MASK … #define MTL_RPN_CAP_MASK … #define MTL_GT_RPE_FREQUENCY … #define MTL_MPE_FREQUENCY … #define MTL_RPE_MASK … #define GT0_PERF_LIMIT_REASONS … #define GT0_PERF_LIMIT_REASONS_MASK … #define PROCHOT_MASK … #define THERMAL_LIMIT_MASK … #define RATL_MASK … #define VR_THERMALERT_MASK … #define VR_TDC_MASK … #define POWER_LIMIT_4_MASK … #define POWER_LIMIT_1_MASK … #define POWER_LIMIT_2_MASK … #define GT0_PERF_LIMIT_REASONS_LOG_MASK … #define MTL_MEDIA_PERF_LIMIT_REASONS … #define CHV_CLK_CTL1 … #define VLV_CLK_CTL2 … #define CLK_CTL2_CZCOUNT_30NS_SHIFT … /* * Overlay regs */ #define OVADD … #define DOVSTA … #define OC_BUF … #define OGAMC5 … #define OGAMC4 … #define OGAMC3 … #define OGAMC2 … #define OGAMC1 … #define OGAMC0 … /* * GEN9 clock gating regs */ #define GEN9_CLKGATE_DIS_0 … #define DARBF_GATING_DIS … #define MTL_PIPEDMC_GATING_DIS_A … #define MTL_PIPEDMC_GATING_DIS_B … #define PWM2_GATING_DIS … #define PWM1_GATING_DIS … #define GEN9_CLKGATE_DIS_3 … #define TGL_VRH_GATING_DIS … #define DPT_GATING_DIS … #define GEN9_CLKGATE_DIS_4 … #define BXT_GMBUS_GATING_DIS … #define GEN9_CLKGATE_DIS_5 … #define DPCE_GATING_DIS … #define _CLKGATE_DIS_PSL_A … #define _CLKGATE_DIS_PSL_B … #define _CLKGATE_DIS_PSL_C … #define DUPS1_GATING_DIS … #define DUPS2_GATING_DIS … #define DUPS3_GATING_DIS … #define CURSOR_GATING_DIS … #define DPF_GATING_DIS … #define DPF_RAM_GATING_DIS … #define DPFR_GATING_DIS … #define CLKGATE_DIS_PSL(pipe) … #define _CLKGATE_DIS_PSL_EXT_A … #define _CLKGATE_DIS_PSL_EXT_B … #define PIPEDMC_GATING_DIS … #define CLKGATE_DIS_PSL_EXT(pipe) … /* DDI Buffer Control */ #define _DDI_CLK_VALFREQ_A … #define _DDI_CLK_VALFREQ_B … #define DDI_CLK_VALFREQ(port) … /* * Display engine regs */ /* Pipe/transcoder A timing regs */ #define _TRANS_HTOTAL_A … #define HTOTAL_MASK … #define HTOTAL(htotal) … #define HACTIVE_MASK … #define HACTIVE(hdisplay) … #define _TRANS_HBLANK_A … #define HBLANK_END_MASK … #define HBLANK_END(hblank_end) … #define HBLANK_START_MASK … #define HBLANK_START(hblank_start) … #define _TRANS_HSYNC_A … #define HSYNC_END_MASK … #define HSYNC_END(hsync_end) … #define HSYNC_START_MASK … #define HSYNC_START(hsync_start) … #define _TRANS_VTOTAL_A … #define VTOTAL_MASK … #define VTOTAL(vtotal) … #define VACTIVE_MASK … #define VACTIVE(vdisplay) … #define _TRANS_VBLANK_A … #define VBLANK_END_MASK … #define VBLANK_END(vblank_end) … #define VBLANK_START_MASK … #define VBLANK_START(vblank_start) … #define _TRANS_VSYNC_A … #define VSYNC_END_MASK … #define VSYNC_END(vsync_end) … #define VSYNC_START_MASK … #define VSYNC_START(vsync_start) … #define _TRANS_EXITLINE_A … #define _PIPEASRC … #define PIPESRC_WIDTH_MASK … #define PIPESRC_WIDTH(w) … #define PIPESRC_HEIGHT_MASK … #define PIPESRC_HEIGHT(h) … #define _BCLRPAT_A … #define _TRANS_VSYNCSHIFT_A … #define _TRANS_MULT_A … /* Pipe/transcoder B timing regs */ #define _TRANS_HTOTAL_B … #define _TRANS_HBLANK_B … #define _TRANS_HSYNC_B … #define _TRANS_VTOTAL_B … #define _TRANS_VBLANK_B … #define _TRANS_VSYNC_B … #define _PIPEBSRC … #define _BCLRPAT_B … #define _TRANS_VSYNCSHIFT_B … #define _TRANS_MULT_B … /* DSI 0 timing regs */ #define _TRANS_HTOTAL_DSI0 … #define _TRANS_HSYNC_DSI0 … #define _TRANS_VTOTAL_DSI0 … #define _TRANS_VSYNC_DSI0 … #define _TRANS_VSYNCSHIFT_DSI0 … /* DSI 1 timing regs */ #define _TRANS_HTOTAL_DSI1 … #define _TRANS_HSYNC_DSI1 … #define _TRANS_VTOTAL_DSI1 … #define _TRANS_VSYNC_DSI1 … #define _TRANS_VSYNCSHIFT_DSI1 … #define TRANS_HTOTAL(dev_priv, trans) … #define TRANS_HBLANK(dev_priv, trans) … #define TRANS_HSYNC(dev_priv, trans) … #define TRANS_VTOTAL(dev_priv, trans) … #define TRANS_VBLANK(dev_priv, trans) … #define TRANS_VSYNC(dev_priv, trans) … #define BCLRPAT(dev_priv, trans) … #define TRANS_VSYNCSHIFT(dev_priv, trans) … #define PIPESRC(dev_priv, pipe) … #define TRANS_MULT(dev_priv, trans) … /* VGA port control */ #define ADPA … #define PCH_ADPA … #define VLV_ADPA … #define ADPA_DAC_ENABLE … #define ADPA_DAC_DISABLE … #define ADPA_PIPE_SEL_SHIFT … #define ADPA_PIPE_SEL_MASK … #define ADPA_PIPE_SEL(pipe) … #define ADPA_PIPE_SEL_SHIFT_CPT … #define ADPA_PIPE_SEL_MASK_CPT … #define ADPA_PIPE_SEL_CPT(pipe) … #define ADPA_CRT_HOTPLUG_MASK … #define ADPA_CRT_HOTPLUG_MONITOR_NONE … #define ADPA_CRT_HOTPLUG_MONITOR_MASK … #define ADPA_CRT_HOTPLUG_MONITOR_COLOR … #define ADPA_CRT_HOTPLUG_MONITOR_MONO … #define ADPA_CRT_HOTPLUG_ENABLE … #define ADPA_CRT_HOTPLUG_PERIOD_64 … #define ADPA_CRT_HOTPLUG_PERIOD_128 … #define ADPA_CRT_HOTPLUG_WARMUP_5MS … #define ADPA_CRT_HOTPLUG_WARMUP_10MS … #define ADPA_CRT_HOTPLUG_SAMPLE_2S … #define ADPA_CRT_HOTPLUG_SAMPLE_4S … #define ADPA_CRT_HOTPLUG_VOLTAGE_40 … #define ADPA_CRT_HOTPLUG_VOLTAGE_50 … #define ADPA_CRT_HOTPLUG_VOLTAGE_60 … #define ADPA_CRT_HOTPLUG_VOLTAGE_70 … #define ADPA_CRT_HOTPLUG_VOLREF_325MV … #define ADPA_CRT_HOTPLUG_VOLREF_475MV … #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER … #define ADPA_USE_VGA_HVPOLARITY … #define ADPA_SETS_HVPOLARITY … #define ADPA_VSYNC_CNTL_DISABLE … #define ADPA_VSYNC_CNTL_ENABLE … #define ADPA_HSYNC_CNTL_DISABLE … #define ADPA_HSYNC_CNTL_ENABLE … #define ADPA_VSYNC_ACTIVE_HIGH … #define ADPA_VSYNC_ACTIVE_LOW … #define ADPA_HSYNC_ACTIVE_HIGH … #define ADPA_HSYNC_ACTIVE_LOW … #define ADPA_DPMS_MASK … #define ADPA_DPMS_ON … #define ADPA_DPMS_SUSPEND … #define ADPA_DPMS_STANDBY … #define ADPA_DPMS_OFF … /* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN(dev_priv) … #define PORTB_HOTPLUG_INT_EN … #define PORTC_HOTPLUG_INT_EN … #define PORTD_HOTPLUG_INT_EN … #define SDVOB_HOTPLUG_INT_EN … #define SDVOC_HOTPLUG_INT_EN … #define TV_HOTPLUG_INT_EN … #define CRT_HOTPLUG_INT_EN … #define HOTPLUG_INT_EN_MASK … #define CRT_HOTPLUG_FORCE_DETECT … #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 … /* must use period 64 on GM45 according to docs */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 … #define CRT_HOTPLUG_DAC_ON_TIME_2M … #define CRT_HOTPLUG_DAC_ON_TIME_4M … #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 … #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK … #define CRT_HOTPLUG_DETECT_DELAY_1G … #define CRT_HOTPLUG_DETECT_DELAY_2G … #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV … #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV … #define PORT_HOTPLUG_STAT(dev_priv) … /* HDMI/DP bits are g4x+ */ #define PORTD_HOTPLUG_LIVE_STATUS_G4X … #define PORTC_HOTPLUG_LIVE_STATUS_G4X … #define PORTB_HOTPLUG_LIVE_STATUS_G4X … #define PORTD_HOTPLUG_INT_STATUS … #define PORTD_HOTPLUG_INT_LONG_PULSE … #define PORTD_HOTPLUG_INT_SHORT_PULSE … #define PORTC_HOTPLUG_INT_STATUS … #define PORTC_HOTPLUG_INT_LONG_PULSE … #define PORTC_HOTPLUG_INT_SHORT_PULSE … #define PORTB_HOTPLUG_INT_STATUS … #define PORTB_HOTPLUG_INT_LONG_PULSE … #define PORTB_HOTPLUG_INT_SHORT_PLUSE … /* CRT/TV common between gen3+ */ #define CRT_HOTPLUG_INT_STATUS … #define TV_HOTPLUG_INT_STATUS … #define CRT_HOTPLUG_MONITOR_MASK … #define CRT_HOTPLUG_MONITOR_COLOR … #define CRT_HOTPLUG_MONITOR_MONO … #define CRT_HOTPLUG_MONITOR_NONE … #define DP_AUX_CHANNEL_D_INT_STATUS_G4X … #define DP_AUX_CHANNEL_C_INT_STATUS_G4X … #define DP_AUX_CHANNEL_B_INT_STATUS_G4X … #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X … /* SDVO is different across gen3/4 */ #define SDVOC_HOTPLUG_INT_STATUS_G4X … #define SDVOB_HOTPLUG_INT_STATUS_G4X … /* * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, * since reality corrobates that they're the same as on gen3. But keep these * bits here (and the comment!) to help any other lost wanderers back onto the * right tracks. */ #define SDVOC_HOTPLUG_INT_STATUS_I965 … #define SDVOB_HOTPLUG_INT_STATUS_I965 … #define SDVOC_HOTPLUG_INT_STATUS_I915 … #define SDVOB_HOTPLUG_INT_STATUS_I915 … #define HOTPLUG_INT_STATUS_G4X … #define HOTPLUG_INT_STATUS_I915 … /* SDVO and HDMI port control. * The same register may be used for SDVO or HDMI */ #define _GEN3_SDVOB … #define _GEN3_SDVOC … #define GEN3_SDVOB … #define GEN3_SDVOC … #define GEN4_HDMIB … #define GEN4_HDMIC … #define VLV_HDMIB … #define VLV_HDMIC … #define CHV_HDMID … #define PCH_SDVOB … #define PCH_HDMIB … #define PCH_HDMIC … #define PCH_HDMID … #define PORT_DFT_I9XX … #define DC_BALANCE_RESET … #define PORT_DFT2_G4X(dev_priv) … #define DC_BALANCE_RESET_VLV … #define PIPE_SCRAMBLE_RESET_MASK … #define PIPE_C_SCRAMBLE_RESET … #define PIPE_B_SCRAMBLE_RESET … #define PIPE_A_SCRAMBLE_RESET … /* Gen 3 SDVO bits: */ #define SDVO_ENABLE … #define SDVO_PIPE_SEL_SHIFT … #define SDVO_PIPE_SEL_MASK … #define SDVO_PIPE_SEL(pipe) … #define SDVO_STALL_SELECT … #define SDVO_INTERRUPT_ENABLE … /* * 915G/GM SDVO pixel multiplier. * Programmed value is multiplier - 1, up to 5x. * \sa DPLL_MD_UDI_MULTIPLIER_MASK */ #define SDVO_PORT_MULTIPLY_MASK … #define SDVO_PORT_MULTIPLY_SHIFT … #define SDVO_PHASE_SELECT_MASK … #define SDVO_PHASE_SELECT_DEFAULT … #define SDVO_CLOCK_OUTPUT_INVERT … #define SDVOC_GANG_MODE … #define SDVO_BORDER_ENABLE … #define SDVOB_PCIE_CONCURRENCY … #define SDVO_DETECTED … /* Bits to be preserved when writing */ #define SDVOB_PRESERVE_MASK … #define SDVOC_PRESERVE_MASK … /* Gen 4 SDVO/HDMI bits: */ #define SDVO_COLOR_FORMAT_8bpc … #define SDVO_COLOR_FORMAT_MASK … #define SDVO_ENCODING_SDVO … #define SDVO_ENCODING_HDMI … #define HDMI_MODE_SELECT_HDMI … #define HDMI_MODE_SELECT_DVI … #define HDMI_COLOR_RANGE_16_235 … #define HDMI_AUDIO_ENABLE … /* VSYNC/HSYNC bits new with 965, default is to be set */ #define SDVO_VSYNC_ACTIVE_HIGH … #define SDVO_HSYNC_ACTIVE_HIGH … /* Gen 5 (IBX) SDVO/HDMI bits: */ #define HDMI_COLOR_FORMAT_12bpc … #define SDVOB_HOTPLUG_ENABLE … /* Gen 6 (CPT) SDVO/HDMI bits: */ #define SDVO_PIPE_SEL_SHIFT_CPT … #define SDVO_PIPE_SEL_MASK_CPT … #define SDVO_PIPE_SEL_CPT(pipe) … /* CHV SDVO/HDMI bits: */ #define SDVO_PIPE_SEL_SHIFT_CHV … #define SDVO_PIPE_SEL_MASK_CHV … #define SDVO_PIPE_SEL_CHV(pipe) … /* Video Data Island Packet control */ #define VIDEO_DIP_DATA … /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte * of the infoframe structure specified by CEA-861. */ #define VIDEO_DIP_DATA_SIZE … #define VIDEO_DIP_ASYNC_DATA_SIZE … #define VIDEO_DIP_GMP_DATA_SIZE … #define VIDEO_DIP_VSC_DATA_SIZE … #define VIDEO_DIP_PPS_DATA_SIZE … #define VIDEO_DIP_CTL … /* Pre HSW: */ #define VIDEO_DIP_ENABLE … #define VIDEO_DIP_PORT(port) … #define VIDEO_DIP_PORT_MASK … #define VIDEO_DIP_ENABLE_GCP … #define VIDEO_DIP_ENABLE_AVI … #define VIDEO_DIP_ENABLE_VENDOR … #define VIDEO_DIP_ENABLE_GAMUT … #define VIDEO_DIP_ENABLE_SPD … #define VIDEO_DIP_SELECT_AVI … #define VIDEO_DIP_SELECT_VENDOR … #define VIDEO_DIP_SELECT_GAMUT … #define VIDEO_DIP_SELECT_SPD … #define VIDEO_DIP_SELECT_MASK … #define VIDEO_DIP_FREQ_ONCE … #define VIDEO_DIP_FREQ_VSYNC … #define VIDEO_DIP_FREQ_2VSYNC … #define VIDEO_DIP_FREQ_MASK … /* HSW and later: */ #define VIDEO_DIP_ENABLE_DRM_GLK … #define PSR_VSC_BIT_7_SET … #define VSC_SELECT_MASK … #define VSC_SELECT_SHIFT … #define VSC_DIP_HW_HEA_DATA … #define VSC_DIP_HW_HEA_SW_DATA … #define VSC_DIP_HW_DATA_SW_HEA … #define VSC_DIP_SW_HEA_DATA … #define VDIP_ENABLE_PPS … #define VIDEO_DIP_ENABLE_VSC_HSW … #define VIDEO_DIP_ENABLE_GCP_HSW … #define VIDEO_DIP_ENABLE_AVI_HSW … #define VIDEO_DIP_ENABLE_VS_HSW … #define VIDEO_DIP_ENABLE_GMP_HSW … #define VIDEO_DIP_ENABLE_SPD_HSW … /* ADL and later: */ #define VIDEO_DIP_ENABLE_AS_ADL … /* Panel fitting */ #define PFIT_CONTROL(dev_priv) … #define PFIT_ENABLE … #define PFIT_PIPE_MASK … #define PFIT_PIPE(pipe) … #define PFIT_SCALING_MASK … #define PFIT_SCALING_AUTO … #define PFIT_SCALING_PROGRAMMED … #define PFIT_SCALING_PILLAR … #define PFIT_SCALING_LETTER … #define PFIT_FILTER_MASK … #define PFIT_FILTER_FUZZY … #define PFIT_FILTER_CRISP … #define PFIT_FILTER_MEDIAN … #define PFIT_VERT_INTERP_MASK … #define PFIT_VERT_INTERP_BILINEAR … #define PFIT_VERT_AUTO_SCALE … #define PFIT_HORIZ_INTERP_MASK … #define PFIT_HORIZ_INTERP_BILINEAR … #define PFIT_HORIZ_AUTO_SCALE … #define PFIT_PANEL_8TO6_DITHER_ENABLE … #define PFIT_PGM_RATIOS(dev_priv) … #define PFIT_VERT_SCALE_MASK … #define PFIT_VERT_SCALE(x) … #define PFIT_HORIZ_SCALE_MASK … #define PFIT_HORIZ_SCALE(x) … #define PFIT_VERT_SCALE_MASK_965 … #define PFIT_HORIZ_SCALE_MASK_965 … #define PFIT_AUTO_RATIOS(dev_priv) … #define PCH_GTC_CTL … #define PCH_GTC_ENABLE … /* Display Port */ #define DP_A … #define DP_B … #define DP_C … #define DP_D … #define VLV_DP_B … #define VLV_DP_C … #define CHV_DP_D … #define DP_PORT_EN … #define DP_PIPE_SEL_SHIFT … #define DP_PIPE_SEL_MASK … #define DP_PIPE_SEL(pipe) … #define DP_PIPE_SEL_SHIFT_IVB … #define DP_PIPE_SEL_MASK_IVB … #define DP_PIPE_SEL_IVB(pipe) … #define DP_PIPE_SEL_SHIFT_CHV … #define DP_PIPE_SEL_MASK_CHV … #define DP_PIPE_SEL_CHV(pipe) … /* Link training mode - select a suitable mode for each stage */ #define DP_LINK_TRAIN_PAT_1 … #define DP_LINK_TRAIN_PAT_2 … #define DP_LINK_TRAIN_PAT_IDLE … #define DP_LINK_TRAIN_OFF … #define DP_LINK_TRAIN_MASK … #define DP_LINK_TRAIN_SHIFT … /* CPT Link training mode */ #define DP_LINK_TRAIN_PAT_1_CPT … #define DP_LINK_TRAIN_PAT_2_CPT … #define DP_LINK_TRAIN_PAT_IDLE_CPT … #define DP_LINK_TRAIN_OFF_CPT … #define DP_LINK_TRAIN_MASK_CPT … #define DP_LINK_TRAIN_SHIFT_CPT … /* Signal voltages. These are mostly controlled by the other end */ #define DP_VOLTAGE_0_4 … #define DP_VOLTAGE_0_6 … #define DP_VOLTAGE_0_8 … #define DP_VOLTAGE_1_2 … #define DP_VOLTAGE_MASK … #define DP_VOLTAGE_SHIFT … /* Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ #define DP_PRE_EMPHASIS_0 … #define DP_PRE_EMPHASIS_3_5 … #define DP_PRE_EMPHASIS_6 … #define DP_PRE_EMPHASIS_9_5 … #define DP_PRE_EMPHASIS_MASK … #define DP_PRE_EMPHASIS_SHIFT … /* How many wires to use. I guess 3 was too hard */ #define DP_PORT_WIDTH(width) … #define DP_PORT_WIDTH_MASK … #define DP_PORT_WIDTH_SHIFT … /* Mystic DPCD version 1.1 special mode */ #define DP_ENHANCED_FRAMING … /* eDP */ #define DP_PLL_FREQ_270MHZ … #define DP_PLL_FREQ_162MHZ … #define DP_PLL_FREQ_MASK … /* locked once port is enabled */ #define DP_PORT_REVERSAL … /* eDP */ #define DP_PLL_ENABLE … /* sends the clock on lane 15 of the PEG for debug */ #define DP_CLOCK_OUTPUT_ENABLE … #define DP_SCRAMBLING_DISABLE … #define DP_SCRAMBLING_DISABLE_IRONLAKE … /* limit RGB values to avoid confusing TVs */ #define DP_COLOR_RANGE_16_235 … /* Turn on the audio link */ #define DP_AUDIO_OUTPUT_ENABLE … /* vs and hs sync polarity */ #define DP_SYNC_VS_HIGH … #define DP_SYNC_HS_HIGH … /* A fantasy */ #define DP_DETECTED … /* * Computing GMCH M and N values for the Display Port link * * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes * * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) * * The GMCH value is used internally * * bytes_per_pixel is the number of bytes coming out of the plane, * which is after the LUTs, so we want the bytes for our color format. * For our current usage, this is always 3, one byte for R, G and B. */ #define _PIPEA_DATA_M_G4X … #define _PIPEB_DATA_M_G4X … /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ #define TU_SIZE_MASK … #define TU_SIZE(x) … #define DATA_LINK_M_N_MASK … #define DATA_LINK_N_MAX … #define _PIPEA_DATA_N_G4X … #define _PIPEB_DATA_N_G4X … /* * Computing Link M and N values for the Display Port link * * Link M / N = pixel_clock / ls_clk * * (the DP spec calls pixel_clock the 'strm_clk') * * The Link value is transmitted in the Main Stream * Attributes and VB-ID. */ #define _PIPEA_LINK_M_G4X … #define _PIPEB_LINK_M_G4X … #define _PIPEA_LINK_N_G4X … #define _PIPEB_LINK_N_G4X … #define PIPE_DATA_M_G4X(pipe) … #define PIPE_DATA_N_G4X(pipe) … #define PIPE_LINK_M_G4X(pipe) … #define PIPE_LINK_N_G4X(pipe) … /* Pipe A */ #define _PIPEADSL … #define PIPEDSL_CURR_FIELD … #define PIPEDSL_LINE_MASK … #define _TRANSACONF … #define TRANSCONF_ENABLE … #define TRANSCONF_DOUBLE_WIDE … #define TRANSCONF_STATE_ENABLE … #define TRANSCONF_DSI_PLL_LOCKED … #define TRANSCONF_FRAME_START_DELAY_MASK … #define TRANSCONF_FRAME_START_DELAY(x) … #define TRANSCONF_PIPE_LOCKED … #define TRANSCONF_FORCE_BORDER … #define TRANSCONF_GAMMA_MODE_MASK_I9XX … #define TRANSCONF_GAMMA_MODE_MASK_ILK … #define TRANSCONF_GAMMA_MODE_8BIT … #define TRANSCONF_GAMMA_MODE_10BIT … #define TRANSCONF_GAMMA_MODE_12BIT … #define TRANSCONF_GAMMA_MODE_SPLIT … #define TRANSCONF_GAMMA_MODE(x) … #define TRANSCONF_INTERLACE_MASK … #define TRANSCONF_INTERLACE_PROGRESSIVE … #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL … #define TRANSCONF_INTERLACE_W_SYNC_SHIFT … #define TRANSCONF_INTERLACE_W_FIELD_INDICATION … #define TRANSCONF_INTERLACE_FIELD_0_ONLY … /* * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, * DBL=power saving pixel doubling, PF-ID* requires panel fitter */ #define TRANSCONF_INTERLACE_MASK_ILK … #define TRANSCONF_INTERLACE_MASK_HSW … #define TRANSCONF_INTERLACE_PF_PD_ILK … #define TRANSCONF_INTERLACE_PF_ID_ILK … #define TRANSCONF_INTERLACE_IF_ID_ILK … #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK … #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK … #define TRANSCONF_REFRESH_RATE_ALT_ILK … #define TRANSCONF_MSA_TIMING_DELAY_MASK … #define TRANSCONF_MSA_TIMING_DELAY(x) … #define TRANSCONF_CXSR_DOWNCLOCK … #define TRANSCONF_WGC_ENABLE … #define TRANSCONF_REFRESH_RATE_ALT_VLV … #define TRANSCONF_COLOR_RANGE_SELECT … #define TRANSCONF_OUTPUT_COLORSPACE_MASK … #define TRANSCONF_OUTPUT_COLORSPACE_RGB … #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 … #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 … #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW … #define TRANSCONF_BPC_MASK … #define TRANSCONF_BPC_8 … #define TRANSCONF_BPC_10 … #define TRANSCONF_BPC_6 … #define TRANSCONF_BPC_12 … #define TRANSCONF_DITHER_EN … #define TRANSCONF_DITHER_TYPE_MASK … #define TRANSCONF_DITHER_TYPE_SP … #define TRANSCONF_DITHER_TYPE_ST1 … #define TRANSCONF_DITHER_TYPE_ST2 … #define TRANSCONF_DITHER_TYPE_TEMP … #define TRANSCONF_PIXEL_COUNT_SCALING_MASK … #define TRANSCONF_PIXEL_COUNT_SCALING_X4 … #define _PIPEASTAT … #define PIPE_FIFO_UNDERRUN_STATUS … #define SPRITE1_FLIP_DONE_INT_EN_VLV … #define PIPE_CRC_ERROR_ENABLE … #define PIPE_CRC_DONE_ENABLE … #define PERF_COUNTER2_INTERRUPT_EN … #define PIPE_GMBUS_EVENT_ENABLE … #define PLANE_FLIP_DONE_INT_EN_VLV … #define PIPE_HOTPLUG_INTERRUPT_ENABLE … #define PIPE_VSYNC_INTERRUPT_ENABLE … #define PIPE_DISPLAY_LINE_COMPARE_ENABLE … #define PIPE_DPST_EVENT_ENABLE … #define SPRITE0_FLIP_DONE_INT_EN_VLV … #define PIPE_LEGACY_BLC_EVENT_ENABLE … #define PIPE_ODD_FIELD_INTERRUPT_ENABLE … #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE … #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV … #define PERF_COUNTER_INTERRUPT_EN … #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE … #define PIPE_START_VBLANK_INTERRUPT_ENABLE … #define PIPE_FRAMESTART_INTERRUPT_ENABLE … #define PIPE_VBLANK_INTERRUPT_ENABLE … #define PIPEA_HBLANK_INT_EN_VLV … #define PIPE_OVERLAY_UPDATED_ENABLE … #define SPRITE1_FLIP_DONE_INT_STATUS_VLV … #define SPRITE0_FLIP_DONE_INT_STATUS_VLV … #define PIPE_CRC_ERROR_INTERRUPT_STATUS … #define PIPE_CRC_DONE_INTERRUPT_STATUS … #define PERF_COUNTER2_INTERRUPT_STATUS … #define PIPE_GMBUS_INTERRUPT_STATUS … #define PLANE_FLIP_DONE_INT_STATUS_VLV … #define PIPE_HOTPLUG_INTERRUPT_STATUS … #define PIPE_VSYNC_INTERRUPT_STATUS … #define PIPE_DISPLAY_LINE_COMPARE_STATUS … #define PIPE_DPST_EVENT_STATUS … #define PIPE_A_PSR_STATUS_VLV … #define PIPE_LEGACY_BLC_EVENT_STATUS … #define PIPE_ODD_FIELD_INTERRUPT_STATUS … #define PIPE_EVEN_FIELD_INTERRUPT_STATUS … #define PIPE_B_PSR_STATUS_VLV … #define PERF_COUNTER_INTERRUPT_STATUS … #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS … #define PIPE_START_VBLANK_INTERRUPT_STATUS … #define PIPE_FRAMESTART_INTERRUPT_STATUS … #define PIPE_VBLANK_INTERRUPT_STATUS … #define PIPE_HBLANK_INT_STATUS … #define PIPE_OVERLAY_UPDATED_STATUS … #define PIPESTAT_INT_ENABLE_MASK … #define PIPESTAT_INT_STATUS_MASK … #define TRANSCONF(dev_priv, trans) … #define PIPEDSL(dev_priv, pipe) … #define PIPEFRAME(dev_priv, pipe) … #define PIPEFRAMEPIXEL(dev_priv, pipe) … #define PIPESTAT(dev_priv, pipe) … #define _PIPE_ARB_CTL_A … #define PIPE_ARB_CTL(dev_priv, pipe) … #define PIPE_ARB_USE_PROG_SLOTS … #define _PIPE_MISC_A … #define _PIPE_MISC_B … #define PIPE_MISC_YUV420_ENABLE … #define PIPE_MISC_YUV420_MODE_FULL_BLEND … #define PIPE_MISC_HDR_MODE_PRECISION … #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP … #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE … #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE … #define PIPE_MISC_PSR_MASK_CURSOR_MOVE … #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT … #define PIPE_MISC_OUTPUT_COLORSPACE_YUV … #define PIPE_MISC_PIXEL_ROUNDING_TRUNC … /* * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with * valid values of: 6, 8, 10 BPC. * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: * 6, 8, 10, 12 BPC. */ #define PIPE_MISC_BPC_MASK … #define PIPE_MISC_BPC_8 … #define PIPE_MISC_BPC_10 … #define PIPE_MISC_BPC_6 … #define PIPE_MISC_BPC_12_ADLP … #define PIPE_MISC_DITHER_ENABLE … #define PIPE_MISC_DITHER_TYPE_MASK … #define PIPE_MISC_DITHER_TYPE_SP … #define PIPE_MISC_DITHER_TYPE_ST1 … #define PIPE_MISC_DITHER_TYPE_ST2 … #define PIPE_MISC_DITHER_TYPE_TEMP … #define PIPE_MISC(pipe) … #define _PIPE_MISC2_A … #define _PIPE_MISC2_B … #define PIPE_MISC2_BUBBLE_COUNTER_MASK … #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN … #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS … #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK … #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) … #define PIPE_MISC2(pipe) … #define _ICL_PIPE_A_STATUS … #define ICL_PIPESTATUS(dev_priv, pipe) … #define PIPE_STATUS_UNDERRUN … #define PIPE_STATUS_SOFT_UNDERRUN_XELPD … #define PIPE_STATUS_HARD_UNDERRUN_XELPD … #define PIPE_STATUS_PORT_UNDERRUN_XELPD … #define VLV_DPFLIPSTAT … #define PIPEB_LINE_COMPARE_INT_EN … #define PIPEB_HLINE_INT_EN … #define PIPEB_VBLANK_INT_EN … #define SPRITED_FLIP_DONE_INT_EN … #define SPRITEC_FLIP_DONE_INT_EN … #define PLANEB_FLIP_DONE_INT_EN … #define PIPE_PSR_INT_EN … #define PIPEA_LINE_COMPARE_INT_EN … #define PIPEA_HLINE_INT_EN … #define PIPEA_VBLANK_INT_EN … #define SPRITEB_FLIP_DONE_INT_EN … #define SPRITEA_FLIP_DONE_INT_EN … #define PLANEA_FLIPDONE_INT_EN … #define PIPEC_LINE_COMPARE_INT_EN … #define PIPEC_HLINE_INT_EN … #define PIPEC_VBLANK_INT_EN … #define SPRITEF_FLIPDONE_INT_EN … #define SPRITEE_FLIPDONE_INT_EN … #define PLANEC_FLIPDONE_INT_EN … #define DPINVGTT … #define DPINVGTT_EN_MASK_CHV … #define DPINVGTT_EN_MASK_VLV … #define SPRITEF_INVALID_GTT_INT_EN … #define SPRITEE_INVALID_GTT_INT_EN … #define PLANEC_INVALID_GTT_INT_EN … #define CURSORC_INVALID_GTT_INT_EN … #define CURSORB_INVALID_GTT_INT_EN … #define CURSORA_INVALID_GTT_INT_EN … #define SPRITED_INVALID_GTT_INT_EN … #define SPRITEC_INVALID_GTT_INT_EN … #define PLANEB_INVALID_GTT_INT_EN … #define SPRITEB_INVALID_GTT_INT_EN … #define SPRITEA_INVALID_GTT_INT_EN … #define PLANEA_INVALID_GTT_INT_EN … #define DPINVGTT_STATUS_MASK_CHV … #define DPINVGTT_STATUS_MASK_VLV … #define SPRITEF_INVALID_GTT_STATUS … #define SPRITEE_INVALID_GTT_STATUS … #define PLANEC_INVALID_GTT_STATUS … #define CURSORC_INVALID_GTT_STATUS … #define CURSORB_INVALID_GTT_STATUS … #define CURSORA_INVALID_GTT_STATUS … #define SPRITED_INVALID_GTT_STATUS … #define SPRITEC_INVALID_GTT_STATUS … #define PLANEB_INVALID_GTT_STATUS … #define SPRITEB_INVALID_GTT_STATUS … #define SPRITEA_INVALID_GTT_STATUS … #define PLANEA_INVALID_GTT_STATUS … #define DSPARB(dev_priv) … #define DSPARB_CSTART_MASK … #define DSPARB_CSTART_SHIFT … #define DSPARB_BSTART_MASK … #define DSPARB_BSTART_SHIFT … #define DSPARB_BEND_SHIFT … #define DSPARB_AEND_SHIFT … #define DSPARB_SPRITEA_SHIFT_VLV … #define DSPARB_SPRITEA_MASK_VLV … #define DSPARB_SPRITEB_SHIFT_VLV … #define DSPARB_SPRITEB_MASK_VLV … #define DSPARB_SPRITEC_SHIFT_VLV … #define DSPARB_SPRITEC_MASK_VLV … #define DSPARB_SPRITED_SHIFT_VLV … #define DSPARB_SPRITED_MASK_VLV … #define DSPARB2 … #define DSPARB_SPRITEA_HI_SHIFT_VLV … #define DSPARB_SPRITEA_HI_MASK_VLV … #define DSPARB_SPRITEB_HI_SHIFT_VLV … #define DSPARB_SPRITEB_HI_MASK_VLV … #define DSPARB_SPRITEC_HI_SHIFT_VLV … #define DSPARB_SPRITEC_HI_MASK_VLV … #define DSPARB_SPRITED_HI_SHIFT_VLV … #define DSPARB_SPRITED_HI_MASK_VLV … #define DSPARB_SPRITEE_HI_SHIFT_VLV … #define DSPARB_SPRITEE_HI_MASK_VLV … #define DSPARB_SPRITEF_HI_SHIFT_VLV … #define DSPARB_SPRITEF_HI_MASK_VLV … #define DSPARB3 … #define DSPARB_SPRITEE_SHIFT_VLV … #define DSPARB_SPRITEE_MASK_VLV … #define DSPARB_SPRITEF_SHIFT_VLV … #define DSPARB_SPRITEF_MASK_VLV … /* pnv/gen4/g4x/vlv/chv */ #define DSPFW1(dev_priv) … #define DSPFW_SR_SHIFT … #define DSPFW_SR_MASK … #define DSPFW_CURSORB_SHIFT … #define DSPFW_CURSORB_MASK … #define DSPFW_PLANEB_SHIFT … #define DSPFW_PLANEB_MASK … #define DSPFW_PLANEB_MASK_VLV … #define DSPFW_PLANEA_SHIFT … #define DSPFW_PLANEA_MASK … #define DSPFW_PLANEA_MASK_VLV … #define DSPFW2(dev_priv) … #define DSPFW_FBC_SR_EN … #define DSPFW_FBC_SR_SHIFT … #define DSPFW_FBC_SR_MASK … #define DSPFW_FBC_HPLL_SR_SHIFT … #define DSPFW_FBC_HPLL_SR_MASK … #define DSPFW_SPRITEB_SHIFT … #define DSPFW_SPRITEB_MASK … #define DSPFW_SPRITEB_MASK_VLV … #define DSPFW_CURSORA_SHIFT … #define DSPFW_CURSORA_MASK … #define DSPFW_PLANEC_OLD_SHIFT … #define DSPFW_PLANEC_OLD_MASK … #define DSPFW_SPRITEA_SHIFT … #define DSPFW_SPRITEA_MASK … #define DSPFW_SPRITEA_MASK_VLV … #define DSPFW3(dev_priv) … #define DSPFW_HPLL_SR_EN … #define PINEVIEW_SELF_REFRESH_EN … #define DSPFW_CURSOR_SR_SHIFT … #define DSPFW_CURSOR_SR_MASK … #define DSPFW_HPLL_CURSOR_SHIFT … #define DSPFW_HPLL_CURSOR_MASK … #define DSPFW_HPLL_SR_SHIFT … #define DSPFW_HPLL_SR_MASK … /* vlv/chv */ #define DSPFW4 … #define DSPFW_SPRITEB_WM1_SHIFT … #define DSPFW_SPRITEB_WM1_MASK … #define DSPFW_CURSORA_WM1_SHIFT … #define DSPFW_CURSORA_WM1_MASK … #define DSPFW_SPRITEA_WM1_SHIFT … #define DSPFW_SPRITEA_WM1_MASK … #define DSPFW5 … #define DSPFW_PLANEB_WM1_SHIFT … #define DSPFW_PLANEB_WM1_MASK … #define DSPFW_PLANEA_WM1_SHIFT … #define DSPFW_PLANEA_WM1_MASK … #define DSPFW_CURSORB_WM1_SHIFT … #define DSPFW_CURSORB_WM1_MASK … #define DSPFW_CURSOR_SR_WM1_SHIFT … #define DSPFW_CURSOR_SR_WM1_MASK … #define DSPFW6 … #define DSPFW_SR_WM1_SHIFT … #define DSPFW_SR_WM1_MASK … #define DSPFW7 … #define DSPFW7_CHV … #define DSPFW_SPRITED_WM1_SHIFT … #define DSPFW_SPRITED_WM1_MASK … #define DSPFW_SPRITED_SHIFT … #define DSPFW_SPRITED_MASK_VLV … #define DSPFW_SPRITEC_WM1_SHIFT … #define DSPFW_SPRITEC_WM1_MASK … #define DSPFW_SPRITEC_SHIFT … #define DSPFW_SPRITEC_MASK_VLV … #define DSPFW8_CHV … #define DSPFW_SPRITEF_WM1_SHIFT … #define DSPFW_SPRITEF_WM1_MASK … #define DSPFW_SPRITEF_SHIFT … #define DSPFW_SPRITEF_MASK_VLV … #define DSPFW_SPRITEE_WM1_SHIFT … #define DSPFW_SPRITEE_WM1_MASK … #define DSPFW_SPRITEE_SHIFT … #define DSPFW_SPRITEE_MASK_VLV … #define DSPFW9_CHV … #define DSPFW_PLANEC_WM1_SHIFT … #define DSPFW_PLANEC_WM1_MASK … #define DSPFW_PLANEC_SHIFT … #define DSPFW_PLANEC_MASK_VLV … #define DSPFW_CURSORC_WM1_SHIFT … #define DSPFW_CURSORC_WM1_MASK … #define DSPFW_CURSORC_SHIFT … #define DSPFW_CURSORC_MASK … /* vlv/chv high order bits */ #define DSPHOWM … #define DSPFW_SR_HI_SHIFT … #define DSPFW_SR_HI_MASK … #define DSPFW_SPRITEF_HI_SHIFT … #define DSPFW_SPRITEF_HI_MASK … #define DSPFW_SPRITEE_HI_SHIFT … #define DSPFW_SPRITEE_HI_MASK … #define DSPFW_PLANEC_HI_SHIFT … #define DSPFW_PLANEC_HI_MASK … #define DSPFW_SPRITED_HI_SHIFT … #define DSPFW_SPRITED_HI_MASK … #define DSPFW_SPRITEC_HI_SHIFT … #define DSPFW_SPRITEC_HI_MASK … #define DSPFW_PLANEB_HI_SHIFT … #define DSPFW_PLANEB_HI_MASK … #define DSPFW_SPRITEB_HI_SHIFT … #define DSPFW_SPRITEB_HI_MASK … #define DSPFW_SPRITEA_HI_SHIFT … #define DSPFW_SPRITEA_HI_MASK … #define DSPFW_PLANEA_HI_SHIFT … #define DSPFW_PLANEA_HI_MASK … #define DSPHOWM1 … #define DSPFW_SR_WM1_HI_SHIFT … #define DSPFW_SR_WM1_HI_MASK … #define DSPFW_SPRITEF_WM1_HI_SHIFT … #define DSPFW_SPRITEF_WM1_HI_MASK … #define DSPFW_SPRITEE_WM1_HI_SHIFT … #define DSPFW_SPRITEE_WM1_HI_MASK … #define DSPFW_PLANEC_WM1_HI_SHIFT … #define DSPFW_PLANEC_WM1_HI_MASK … #define DSPFW_SPRITED_WM1_HI_SHIFT … #define DSPFW_SPRITED_WM1_HI_MASK … #define DSPFW_SPRITEC_WM1_HI_SHIFT … #define DSPFW_SPRITEC_WM1_HI_MASK … #define DSPFW_PLANEB_WM1_HI_SHIFT … #define DSPFW_PLANEB_WM1_HI_MASK … #define DSPFW_SPRITEB_WM1_HI_SHIFT … #define DSPFW_SPRITEB_WM1_HI_MASK … #define DSPFW_SPRITEA_WM1_HI_SHIFT … #define DSPFW_SPRITEA_WM1_HI_MASK … #define DSPFW_PLANEA_WM1_HI_SHIFT … #define DSPFW_PLANEA_WM1_HI_MASK … /* drain latency register values*/ #define VLV_DDL(pipe) … #define DDL_CURSOR_SHIFT … #define DDL_SPRITE_SHIFT(sprite) … #define DDL_PLANE_SHIFT … #define DDL_PRECISION_HIGH … #define DDL_PRECISION_LOW … #define DRAIN_LATENCY_MASK … #define CBR1_VLV … #define CBR_PND_DEADLINE_DISABLE … #define CBR_PWM_CLOCK_MUX_SELECT … #define CBR4_VLV … #define CBR_DPLLBMD_PIPE(pipe) … /* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE … #define I915_FIFO_LINE_SIZE … #define I830_FIFO_LINE_SIZE … #define VALLEYVIEW_FIFO_SIZE … #define G4X_FIFO_SIZE … #define I965_FIFO_SIZE … #define I945_FIFO_SIZE … #define I915_FIFO_SIZE … #define I855GM_FIFO_SIZE … #define I830_FIFO_SIZE … #define VALLEYVIEW_MAX_WM … #define G4X_MAX_WM … #define I915_MAX_WM … #define PINEVIEW_DISPLAY_FIFO … #define PINEVIEW_FIFO_LINE_SIZE … #define PINEVIEW_MAX_WM … #define PINEVIEW_DFT_WM … #define PINEVIEW_DFT_HPLLOFF_WM … #define PINEVIEW_GUARD_WM … #define PINEVIEW_CURSOR_FIFO … #define PINEVIEW_CURSOR_MAX_WM … #define PINEVIEW_CURSOR_DFT_WM … #define PINEVIEW_CURSOR_GUARD_WM … #define VALLEYVIEW_CURSOR_MAX_WM … #define I965_CURSOR_FIFO … #define I965_CURSOR_MAX_WM … #define I965_CURSOR_DFT_WM … /* define the Watermark register on Ironlake */ #define _WM0_PIPEA_ILK … #define _WM0_PIPEB_ILK … #define _WM0_PIPEC_IVB … #define WM0_PIPE_ILK(pipe) … #define WM0_PIPE_PRIMARY_MASK … #define WM0_PIPE_SPRITE_MASK … #define WM0_PIPE_CURSOR_MASK … #define WM0_PIPE_PRIMARY(x) … #define WM0_PIPE_SPRITE(x) … #define WM0_PIPE_CURSOR(x) … #define WM1_LP_ILK … #define WM2_LP_ILK … #define WM3_LP_ILK … #define WM_LP_ENABLE … #define WM_LP_LATENCY_MASK … #define WM_LP_FBC_MASK_BDW … #define WM_LP_FBC_MASK_ILK … #define WM_LP_PRIMARY_MASK … #define WM_LP_CURSOR_MASK … #define WM_LP_LATENCY(x) … #define WM_LP_FBC_BDW(x) … #define WM_LP_FBC_ILK(x) … #define WM_LP_PRIMARY(x) … #define WM_LP_CURSOR(x) … #define WM1S_LP_ILK … #define WM2S_LP_IVB … #define WM3S_LP_IVB … #define WM_LP_SPRITE_ENABLE … #define WM_LP_SPRITE_MASK … #define WM_LP_SPRITE(x) … /* * The two pipe frame counter registers are not synchronized, so * reading a stable value is somewhat tricky. The following code * should work: * * do { * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> * PIPE_FRAME_HIGH_SHIFT; * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> * PIPE_FRAME_LOW_SHIFT); * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> * PIPE_FRAME_HIGH_SHIFT); * } while (high1 != high2); * frame = (high1 << 8) | low1; */ #define _PIPEAFRAMEHIGH … #define PIPE_FRAME_HIGH_MASK … #define PIPE_FRAME_HIGH_SHIFT … #define _PIPEAFRAMEPIXEL … #define PIPE_FRAME_LOW_MASK … #define PIPE_FRAME_LOW_SHIFT … #define PIPE_PIXEL_MASK … #define PIPE_PIXEL_SHIFT … /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_G4X … #define _PIPEA_FLIPCOUNT_G4X … #define PIPE_FRMCOUNT_G4X(dev_priv, pipe) … #define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) … /* CHV pipe B blender */ #define _CHV_BLEND_A … #define CHV_BLEND_MASK … #define CHV_BLEND_LEGACY … #define CHV_BLEND_ANDROID … #define CHV_BLEND_MPO … #define _CHV_CANVAS_A … #define CHV_CANVAS_RED_MASK … #define CHV_CANVAS_GREEN_MASK … #define CHV_CANVAS_BLUE_MASK … #define CHV_BLEND(dev_priv, pipe) … #define CHV_CANVAS(dev_priv, pipe) … /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK … #define I915_LO_DISPBASE(val) … #define I915_HI_DISPBASE(val) … /* * VBIOS flags * gen2: * [00:06] alm,mgm * [10:16] all * [30:32] alm,mgm * gen3+: * [00:0f] all * [10:1f] all * [30:32] all */ #define SWF0(dev_priv, i) … #define SWF1(dev_priv, i) … #define SWF3(dev_priv, i) … #define SWF_ILK(i) … /* ICL DSI 0 and 1 */ #define _PIPEDSI0CONF … #define _PIPEDSI1CONF … /* VBIOS regs */ #define VGACNTRL … #define VGA_DISP_DISABLE … #define VGA_2X_MODE … #define VGA_PIPE_B_SELECT … #define VLV_VGACNTRL … /* Ironlake */ #define CPU_VGACNTRL … #define DIGITAL_PORT_HOTPLUG_CNTRL … #define DIGITAL_PORTA_HOTPLUG_ENABLE … #define DIGITAL_PORTA_PULSE_DURATION_2ms … #define DIGITAL_PORTA_PULSE_DURATION_4_5ms … #define DIGITAL_PORTA_PULSE_DURATION_6ms … #define DIGITAL_PORTA_PULSE_DURATION_100ms … #define DIGITAL_PORTA_PULSE_DURATION_MASK … #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK … #define DIGITAL_PORTA_HOTPLUG_NO_DETECT … #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT … #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT … /* refresh rate hardware control */ #define RR_HW_CTL … #define RR_HW_LOW_POWER_FRAMES_MASK … #define RR_HW_HIGH_POWER_FRAMES_MASK … #define PCH_3DCGDIS0 … #define MARIUNIT_CLOCK_GATE_DISABLE … #define SVSMUNIT_CLOCK_GATE_DISABLE … #define PCH_3DCGDIS1 … #define VFMUNIT_CLOCK_GATE_DISABLE … #define _PIPEA_DATA_M1 … #define _PIPEA_DATA_N1 … #define _PIPEA_DATA_M2 … #define _PIPEA_DATA_N2 … #define _PIPEA_LINK_M1 … #define _PIPEA_LINK_N1 … #define _PIPEA_LINK_M2 … #define _PIPEA_LINK_N2 … /* PIPEB timing regs are same start from 0x61000 */ #define _PIPEB_DATA_M1 … #define _PIPEB_DATA_N1 … #define _PIPEB_DATA_M2 … #define _PIPEB_DATA_N2 … #define _PIPEB_LINK_M1 … #define _PIPEB_LINK_N1 … #define _PIPEB_LINK_M2 … #define _PIPEB_LINK_N2 … #define PIPE_DATA_M1(dev_priv, tran) … #define PIPE_DATA_N1(dev_priv, tran) … #define PIPE_DATA_M2(dev_priv, tran) … #define PIPE_DATA_N2(dev_priv, tran) … #define PIPE_LINK_M1(dev_priv, tran) … #define PIPE_LINK_N1(dev_priv, tran) … #define PIPE_LINK_M2(dev_priv, tran) … #define PIPE_LINK_N2(dev_priv, tran) … /* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ #define _PFA_CTL_1 … #define _PFB_CTL_1 … #define PF_ENABLE … #define PF_PIPE_SEL_MASK_IVB … #define PF_PIPE_SEL_IVB(pipe) … #define PF_FILTER_MASK … #define PF_FILTER_PROGRAMMED … #define PF_FILTER_MED_3x3 … #define PF_FILTER_EDGE_ENHANCE … #define PF_FILTER_EDGE_SOFTEN … #define _PFA_WIN_SZ … #define _PFB_WIN_SZ … #define PF_WIN_XSIZE_MASK … #define PF_WIN_XSIZE(w) … #define PF_WIN_YSIZE_MASK … #define PF_WIN_YSIZE(h) … #define _PFA_WIN_POS … #define _PFB_WIN_POS … #define PF_WIN_XPOS_MASK … #define PF_WIN_XPOS(x) … #define PF_WIN_YPOS_MASK … #define PF_WIN_YPOS(y) … #define _PFA_VSCALE … #define _PFB_VSCALE … #define _PFA_HSCALE … #define _PFB_HSCALE … #define PF_CTL(pipe) … #define PF_WIN_SZ(pipe) … #define PF_WIN_POS(pipe) … #define PF_VSCALE(pipe) … #define PF_HSCALE(pipe) … /* * Skylake scalers */ #define _PS_1A_CTRL … #define _PS_2A_CTRL … #define _PS_1B_CTRL … #define _PS_2B_CTRL … #define _PS_1C_CTRL … #define PS_SCALER_EN … #define PS_SCALER_TYPE_MASK … #define PS_SCALER_TYPE_NON_LINEAR … #define PS_SCALER_TYPE_LINEAR … #define SKL_PS_SCALER_MODE_MASK … #define SKL_PS_SCALER_MODE_DYN … #define SKL_PS_SCALER_MODE_HQ … #define SKL_PS_SCALER_MODE_NV12 … #define PS_SCALER_MODE_MASK … #define PS_SCALER_MODE_NORMAL … #define PS_SCALER_MODE_PLANAR … #define PS_ADAPTIVE_FILTERING_EN … #define PS_BINDING_MASK … #define PS_BINDING_PIPE … #define PS_BINDING_PLANE(plane_id) … #define PS_FILTER_MASK … #define PS_FILTER_MEDIUM … #define PS_FILTER_PROGRAMMED … #define PS_FILTER_EDGE_ENHANCE … #define PS_FILTER_BILINEAR … #define PS_ADAPTIVE_FILTER_MASK … #define PS_ADAPTIVE_FILTER_MEDIUM … #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE … #define PS_PIPE_SCALER_LOC_MASK … #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC … #define PS_PIPE_SCALER_LOC_AFTER_CSC … #define PS_VERT3TAP … #define PS_VERT_INT_INVERT_FIELD … #define PS_PROG_SCALE_FACTOR … #define PS_PWRUP_PROGRESS … #define PS_V_FILTER_BYPASS … #define PS_VADAPT_EN … #define PS_VADAPT_MODE_MASK … #define PS_VADAPT_MODE_LEAST_ADAPT … #define PS_VADAPT_MODE_MOD_ADAPT … #define PS_VADAPT_MODE_MOST_ADAPT … #define PS_BINDING_Y_MASK … #define PS_BINDING_Y_PLANE(plane_id) … #define PS_Y_VERT_FILTER_SELECT_MASK … #define PS_Y_VERT_FILTER_SELECT(set) … #define PS_Y_HORZ_FILTER_SELECT_MASK … #define PS_Y_HORZ_FILTER_SELECT(set) … #define PS_UV_VERT_FILTER_SELECT_MASK … #define PS_UV_VERT_FILTER_SELECT(set) … #define PS_UV_HORZ_FILTER_SELECT_MASK … #define PS_UV_HORZ_FILTER_SELECT(set) … #define _PS_PWR_GATE_1A … #define _PS_PWR_GATE_2A … #define _PS_PWR_GATE_1B … #define _PS_PWR_GATE_2B … #define _PS_PWR_GATE_1C … #define PS_PWR_GATE_DIS_OVERRIDE … #define PS_PWR_GATE_SETTLING_TIME_MASK … #define PS_PWR_GATE_SETTLING_TIME_32 … #define PS_PWR_GATE_SETTLING_TIME_64 … #define PS_PWR_GATE_SETTLING_TIME_96 … #define PS_PWR_GATE_SETTLING_TIME_128 … #define PS_PWR_GATE_SLPEN_MASK … #define PS_PWR_GATE_SLPEN_8 … #define PS_PWR_GATE_SLPEN_16 … #define PS_PWR_GATE_SLPEN_24 … #define PS_PWR_GATE_SLPEN_32 … #define _PS_WIN_POS_1A … #define _PS_WIN_POS_2A … #define _PS_WIN_POS_1B … #define _PS_WIN_POS_2B … #define _PS_WIN_POS_1C … #define PS_WIN_XPOS_MASK … #define PS_WIN_XPOS(x) … #define PS_WIN_YPOS_MASK … #define PS_WIN_YPOS(y) … #define _PS_WIN_SZ_1A … #define _PS_WIN_SZ_2A … #define _PS_WIN_SZ_1B … #define _PS_WIN_SZ_2B … #define _PS_WIN_SZ_1C … #define PS_WIN_XSIZE_MASK … #define PS_WIN_XSIZE(w) … #define PS_WIN_YSIZE_MASK … #define PS_WIN_YSIZE(h) … #define _PS_VSCALE_1A … #define _PS_VSCALE_2A … #define _PS_VSCALE_1B … #define _PS_VSCALE_2B … #define _PS_VSCALE_1C … #define _PS_HSCALE_1A … #define _PS_HSCALE_2A … #define _PS_HSCALE_1B … #define _PS_HSCALE_2B … #define _PS_HSCALE_1C … #define _PS_VPHASE_1A … #define _PS_VPHASE_2A … #define _PS_VPHASE_1B … #define _PS_VPHASE_2B … #define _PS_VPHASE_1C … #define PS_Y_PHASE_MASK … #define PS_Y_PHASE(x) … #define PS_UV_RGB_PHASE_MASK … #define PS_UV_RGB_PHASE(x) … #define PS_PHASE_MASK … #define PS_PHASE_TRIP … #define _PS_HPHASE_1A … #define _PS_HPHASE_2A … #define _PS_HPHASE_1B … #define _PS_HPHASE_2B … #define _PS_HPHASE_1C … #define _PS_ECC_STAT_1A … #define _PS_ECC_STAT_2A … #define _PS_ECC_STAT_1B … #define _PS_ECC_STAT_2B … #define _PS_ECC_STAT_1C … #define _PS_COEF_SET0_INDEX_1A … #define _PS_COEF_SET0_INDEX_2A … #define _PS_COEF_SET0_INDEX_1B … #define _PS_COEF_SET0_INDEX_2B … #define PS_COEF_INDEX_AUTO_INC … #define _PS_COEF_SET0_DATA_1A … #define _PS_COEF_SET0_DATA_2A … #define _PS_COEF_SET0_DATA_1B … #define _PS_COEF_SET0_DATA_2B … #define _ID(id, a, b) … #define SKL_PS_CTRL(pipe, id) … #define SKL_PS_PWR_GATE(pipe, id) … #define SKL_PS_WIN_POS(pipe, id) … #define SKL_PS_WIN_SZ(pipe, id) … #define SKL_PS_VSCALE(pipe, id) … #define SKL_PS_HSCALE(pipe, id) … #define SKL_PS_VPHASE(pipe, id) … #define SKL_PS_HPHASE(pipe, id) … #define SKL_PS_ECC_STAT(pipe, id) … #define GLK_PS_COEF_INDEX_SET(pipe, id, set) … #define GLK_PS_COEF_DATA_SET(pipe, id, set) … /* Display Internal Timeout Register */ #define RM_TIMEOUT … #define RM_TIMEOUT_REG_CAPTURE … #define MMIO_TIMEOUT_US(us) … /* interrupts */ #define DE_MASTER_IRQ_CONTROL … #define DE_SPRITEB_FLIP_DONE … #define DE_SPRITEA_FLIP_DONE … #define DE_PLANEB_FLIP_DONE … #define DE_PLANEA_FLIP_DONE … #define DE_PLANE_FLIP_DONE(plane) … #define DE_PCU_EVENT … #define DE_GTT_FAULT … #define DE_POISON … #define DE_PERFORM_COUNTER … #define DE_PCH_EVENT … #define DE_AUX_CHANNEL_A … #define DE_DP_A_HOTPLUG … #define DE_GSE … #define DE_PIPEB_VBLANK … #define DE_PIPEB_EVEN_FIELD … #define DE_PIPEB_ODD_FIELD … #define DE_PIPEB_LINE_COMPARE … #define DE_PIPEB_VSYNC … #define DE_PIPEB_CRC_DONE … #define DE_PIPEB_FIFO_UNDERRUN … #define DE_PIPEA_VBLANK … #define DE_PIPE_VBLANK(pipe) … #define DE_PIPEA_EVEN_FIELD … #define DE_PIPEA_ODD_FIELD … #define DE_PIPEA_LINE_COMPARE … #define DE_PIPEA_VSYNC … #define DE_PIPEA_CRC_DONE … #define DE_PIPE_CRC_DONE(pipe) … #define DE_PIPEA_FIFO_UNDERRUN … #define DE_PIPE_FIFO_UNDERRUN(pipe) … /* More Ivybridge lolz */ #define DE_ERR_INT_IVB … #define DE_GSE_IVB … #define DE_PCH_EVENT_IVB … #define DE_DP_A_HOTPLUG_IVB … #define DE_AUX_CHANNEL_A_IVB … #define DE_EDP_PSR_INT_HSW … #define DE_SPRITEC_FLIP_DONE_IVB … #define DE_PLANEC_FLIP_DONE_IVB … #define DE_PIPEC_VBLANK_IVB … #define DE_SPRITEB_FLIP_DONE_IVB … #define DE_PLANEB_FLIP_DONE_IVB … #define DE_PIPEB_VBLANK_IVB … #define DE_SPRITEA_FLIP_DONE_IVB … #define DE_PLANEA_FLIP_DONE_IVB … #define DE_PLANE_FLIP_DONE_IVB(plane) … #define DE_PIPEA_VBLANK_IVB … #define DE_PIPE_VBLANK_IVB(pipe) … #define VLV_MASTER_IER … #define MASTER_INTERRUPT_ENABLE … #define DEISR … #define DEIMR … #define DEIIR … #define DEIER … #define GTISR … #define GTIMR … #define GTIIR … #define GTIER … #define GEN8_MASTER_IRQ … #define GEN8_MASTER_IRQ_CONTROL … #define GEN8_PCU_IRQ … #define GEN8_DE_PCH_IRQ … #define GEN8_DE_MISC_IRQ … #define GEN8_DE_PORT_IRQ … #define GEN8_DE_PIPE_C_IRQ … #define GEN8_DE_PIPE_B_IRQ … #define GEN8_DE_PIPE_A_IRQ … #define GEN8_DE_PIPE_IRQ(pipe) … #define GEN8_GT_VECS_IRQ … #define GEN8_GT_GUC_IRQ … #define GEN8_GT_PM_IRQ … #define GEN8_GT_VCS1_IRQ … #define GEN8_GT_VCS0_IRQ … #define GEN8_GT_BCS_IRQ … #define GEN8_GT_RCS_IRQ … #define XELPD_DISPLAY_ERR_FATAL_MASK … #define GEN8_GT_ISR(which) … #define GEN8_GT_IMR(which) … #define GEN8_GT_IIR(which) … #define GEN8_GT_IER(which) … #define GEN8_RCS_IRQ_SHIFT … #define GEN8_BCS_IRQ_SHIFT … #define GEN8_VCS0_IRQ_SHIFT … #define GEN8_VCS1_IRQ_SHIFT … #define GEN8_VECS_IRQ_SHIFT … #define GEN8_WD_IRQ_SHIFT … #define GEN8_DE_PIPE_ISR(pipe) … #define GEN8_DE_PIPE_IMR(pipe) … #define GEN8_DE_PIPE_IIR(pipe) … #define GEN8_DE_PIPE_IER(pipe) … #define GEN8_PIPE_FIFO_UNDERRUN … #define GEN8_PIPE_CDCLK_CRC_ERROR … #define GEN8_PIPE_CDCLK_CRC_DONE … #define GEN12_PIPEDMC_INTERRUPT … #define GEN12_PIPEDMC_FAULT … #define MTL_PIPEDMC_ATS_FAULT … #define XELPD_PIPE_SOFT_UNDERRUN … #define GEN11_PIPE_PLANE7_FAULT … #define XELPD_PIPE_HARD_UNDERRUN … #define GEN11_PIPE_PLANE6_FAULT … #define GEN11_PIPE_PLANE5_FAULT … #define GEN12_PIPE_VBLANK_UNMOD … #define MTL_PLANE_ATS_FAULT … #define GEN11_PIPE_PLANE7_FLIP_DONE … #define GEN11_PIPE_PLANE6_FLIP_DONE … #define GEN11_PIPE_PLANE5_FLIP_DONE … #define GEN12_DSB_2_INT … #define GEN12_DSB_1_INT … #define GEN12_DSB_0_INT … #define GEN12_DSB_INT(dsb_id) … #define GEN9_PIPE_CURSOR_FAULT … #define GEN9_PIPE_PLANE4_FAULT … #define GEN8_PIPE_CURSOR_FAULT … #define GEN9_PIPE_PLANE3_FAULT … #define GEN8_PIPE_SPRITE_FAULT … #define GEN9_PIPE_PLANE2_FAULT … #define GEN8_PIPE_PRIMARY_FAULT … #define GEN9_PIPE_PLANE1_FAULT … #define GEN9_PIPE_PLANE4_FLIP_DONE … #define GEN9_PIPE_PLANE3_FLIP_DONE … #define GEN8_PIPE_SPRITE_FLIP_DONE … #define GEN9_PIPE_PLANE2_FLIP_DONE … #define GEN8_PIPE_PRIMARY_FLIP_DONE … #define GEN9_PIPE_PLANE1_FLIP_DONE … #define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) … #define GEN8_PIPE_SCAN_LINE_EVENT … #define GEN8_PIPE_VSYNC … #define GEN8_PIPE_VBLANK … #define _HPD_PIN_DDI(hpd_pin) … #define _HPD_PIN_TC(hpd_pin) … #define GEN8_DE_PORT_ISR … #define GEN8_DE_PORT_IMR … #define GEN8_DE_PORT_IIR … #define GEN8_DE_PORT_IER … #define DSI1_NON_TE … #define DSI0_NON_TE … #define ICL_AUX_CHANNEL_E … #define ICL_AUX_CHANNEL_F … #define GEN9_AUX_CHANNEL_D … #define GEN9_AUX_CHANNEL_C … #define GEN9_AUX_CHANNEL_B … #define DSI1_TE … #define DSI0_TE … #define GEN8_DE_PORT_HOTPLUG(hpd_pin) … #define BXT_DE_PORT_HOTPLUG_MASK … #define BDW_DE_PORT_HOTPLUG_MASK … #define BXT_DE_PORT_GMBUS … #define GEN8_AUX_CHANNEL_A … #define TGL_DE_PORT_AUX_USBC6 … #define XELPD_DE_PORT_AUX_DDIE … #define TGL_DE_PORT_AUX_USBC5 … #define XELPD_DE_PORT_AUX_DDID … #define TGL_DE_PORT_AUX_USBC4 … #define TGL_DE_PORT_AUX_USBC3 … #define TGL_DE_PORT_AUX_USBC2 … #define TGL_DE_PORT_AUX_USBC1 … #define TGL_DE_PORT_AUX_DDIC … #define TGL_DE_PORT_AUX_DDIB … #define TGL_DE_PORT_AUX_DDIA … #define GEN8_DE_MISC_ISR … #define GEN8_DE_MISC_IMR … #define GEN8_DE_MISC_IIR … #define GEN8_DE_MISC_IER … #define XELPDP_RM_TIMEOUT … #define XELPDP_PMDEMAND_RSPTOUT_ERR … #define GEN8_DE_MISC_GSE … #define GEN8_DE_EDP_PSR … #define XELPDP_PMDEMAND_RSP … #define GEN8_PCU_ISR … #define GEN8_PCU_IMR … #define GEN8_PCU_IIR … #define GEN8_PCU_IER … #define GEN11_GU_MISC_ISR … #define GEN11_GU_MISC_IMR … #define GEN11_GU_MISC_IIR … #define GEN11_GU_MISC_IER … #define GEN11_GU_MISC_GSE … #define GEN11_GFX_MSTR_IRQ … #define GEN11_MASTER_IRQ … #define GEN11_PCU_IRQ … #define GEN11_GU_MISC_IRQ … #define GEN11_DISPLAY_IRQ … #define GEN11_GT_DW_IRQ(x) … #define GEN11_GT_DW1_IRQ … #define GEN11_GT_DW0_IRQ … #define DG1_MSTR_TILE_INTR … #define DG1_MSTR_IRQ … #define DG1_MSTR_TILE(t) … #define GEN11_DISPLAY_INT_CTL … #define GEN11_DISPLAY_IRQ_ENABLE … #define GEN11_AUDIO_CODEC_IRQ … #define GEN11_DE_PCH_IRQ … #define GEN11_DE_MISC_IRQ … #define GEN11_DE_HPD_IRQ … #define GEN11_DE_PORT_IRQ … #define GEN11_DE_PIPE_C … #define GEN11_DE_PIPE_B … #define GEN11_DE_PIPE_A … #define GEN11_DE_HPD_ISR … #define GEN11_DE_HPD_IMR … #define GEN11_DE_HPD_IIR … #define GEN11_DE_HPD_IER … #define GEN11_TC_HOTPLUG(hpd_pin) … #define GEN11_DE_TC_HOTPLUG_MASK … #define GEN11_TBT_HOTPLUG(hpd_pin) … #define GEN11_DE_TBT_HOTPLUG_MASK … #define GEN11_TBT_HOTPLUG_CTL … #define GEN11_TC_HOTPLUG_CTL … #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) … #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) … #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) … #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) … #define PICAINTERRUPT_ISR … #define PICAINTERRUPT_IMR … #define PICAINTERRUPT_IIR … #define PICAINTERRUPT_IER … #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) … #define XELPDP_DP_ALT_HOTPLUG_MASK … #define XELPDP_AUX_TC(hpd_pin) … #define XELPDP_AUX_TC_MASK … #define XE2LPD_AUX_DDI(hpd_pin) … #define XE2LPD_AUX_DDI_MASK … #define XELPDP_TBT_HOTPLUG(hpd_pin) … #define XELPDP_TBT_HOTPLUG_MASK … #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) … #define XELPDP_TBT_HOTPLUG_ENABLE … #define XELPDP_TBT_HPD_LONG_DETECT … #define XELPDP_TBT_HPD_SHORT_DETECT … #define XELPDP_DP_ALT_HOTPLUG_ENABLE … #define XELPDP_DP_ALT_HPD_LONG_DETECT … #define XELPDP_DP_ALT_HPD_SHORT_DETECT … #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) … #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK … #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK … #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK … #define XELPDP_PMDEMAND_PIPES_MASK … #define XELPDP_PMDEMAND_DBUFS_MASK … #define XELPDP_PMDEMAND_PHYS_MASK … #define XELPDP_PMDEMAND_REQ_ENABLE … #define XELPDP_PMDEMAND_CDCLK_FREQ_MASK … #define XELPDP_PMDEMAND_DDICLK_FREQ_MASK … #define XELPDP_PMDEMAND_SCALERS_MASK … #define XELPDP_PMDEMAND_PLLS_MASK … #define GEN12_DCPR_STATUS_1 … #define XELPDP_PMDEMAND_INFLIGHT_STATUS … #define ILK_DISPLAY_CHICKEN2 … /* Required on all Ironlake and Sandybridge according to the B-Spec. */ #define ILK_ELPIN_409_SELECT … #define ILK_DPARB_GATE … #define ILK_VSDPFD_FULL … #define FUSE_STRAP … #define ILK_INTERNAL_GRAPHICS_DISABLE … #define ILK_INTERNAL_DISPLAY_DISABLE … #define ILK_DISPLAY_DEBUG_DISABLE … #define IVB_PIPE_C_DISABLE … #define ILK_HDCP_DISABLE … #define ILK_eDP_A_DISABLE … #define HSW_CDCLK_LIMIT … #define ILK_DESKTOP … #define HSW_CPU_SSC_ENABLE … #define FUSE_STRAP3 … #define HSW_REF_CLK_SELECT … #define ILK_DSPCLK_GATE_D … #define ILK_VRHUNIT_CLOCK_GATE_DISABLE … #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE … #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE … #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE … #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE … #define IVB_CHICKEN3 … #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE … #define CHICKEN3_DGMG_DONE_FIX_DISABLE … #define CHICKEN_PAR1_1 … #define IGNORE_KVMR_PIPE_A … #define KBL_ARB_FILL_SPARE_22 … #define DIS_RAM_BYPASS_PSR2_MAN_TRACK … #define SKL_DE_COMPRESSED_HASH_MODE … #define HSW_MASK_VBL_TO_PIPE_IN_SRD … #define FORCE_ARB_IDLE_PLANES … #define SKL_EDP_PSR_FIX_RDWRAP … #define IGNORE_PSR2_HW_TRACKING … #define CHICKEN_PAR2_1 … #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT … #define CHICKEN_MISC_2 … #define CHICKEN_MISC_DISABLE_DPT … #define BMG_DARB_HALF_BLK_END_BURST … #define KBL_ARB_FILL_SPARE_14 … #define KBL_ARB_FILL_SPARE_13 … #define GLK_CL2_PWR_DOWN … #define GLK_CL1_PWR_DOWN … #define GLK_CL0_PWR_DOWN … #define CHICKEN_MISC_3 … #define DP_MST_DPT_DPTP_ALIGN_WA(trans) … #define DP_MST_SHORT_HBLANK_WA(trans) … #define DP_MST_FEC_BS_JITTER_WA(trans) … #define CHICKEN_MISC_4 … #define CHICKEN_FBC_STRIDE_OVERRIDE … #define CHICKEN_FBC_STRIDE_MASK … #define CHICKEN_FBC_STRIDE(x) … #define _CHICKEN_PIPESL_1_A … #define _CHICKEN_PIPESL_1_B … #define CHICKEN_PIPESL_1(pipe) … #define HSW_PRI_STRETCH_MAX_MASK … #define HSW_PRI_STRETCH_MAX_X8 … #define HSW_PRI_STRETCH_MAX_X4 … #define HSW_PRI_STRETCH_MAX_X2 … #define HSW_PRI_STRETCH_MAX_X1 … #define HSW_SPR_STRETCH_MAX_MASK … #define HSW_SPR_STRETCH_MAX_X8 … #define HSW_SPR_STRETCH_MAX_X4 … #define HSW_SPR_STRETCH_MAX_X2 … #define HSW_SPR_STRETCH_MAX_X1 … #define HSW_FBCQ_DIS … #define HSW_UNMASK_VBL_TO_REGS_IN_SRD … #define SKL_PSR_MASK_PLANE_FLIP … #define SKL_PLANE1_STRETCH_MAX_MASK … #define SKL_PLANE1_STRETCH_MAX_X8 … #define SKL_PLANE1_STRETCH_MAX_X4 … #define SKL_PLANE1_STRETCH_MAX_X2 … #define SKL_PLANE1_STRETCH_MAX_X1 … #define BDW_UNMASK_VBL_TO_REGS_IN_SRD … #define _CHICKEN_TRANS_A … #define _CHICKEN_TRANS_B … #define _CHICKEN_TRANS_C … #define _CHICKEN_TRANS_EDP … #define _CHICKEN_TRANS_D … #define CHICKEN_TRANS(trans) … #define _MTL_CHICKEN_TRANS_A … #define _MTL_CHICKEN_TRANS_B … #define MTL_CHICKEN_TRANS(trans) … #define PIPE_VBLANK_WITH_DELAY … #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD … #define HSW_FRAME_START_DELAY_MASK … #define HSW_FRAME_START_DELAY(x) … #define VSC_DATA_SEL_SOFTWARE_CONTROL … #define FECSTALL_DIS_DPTSTREAM_DPTTG … #define DDI_TRAINING_OVERRIDE_ENABLE … #define ADLP_1_BASED_X_GRANULARITY … #define DDI_TRAINING_OVERRIDE_VALUE … #define DDIE_TRAINING_OVERRIDE_ENABLE … #define DDIE_TRAINING_OVERRIDE_VALUE … #define PSR2_ADD_VERTICAL_LINE_COUNT … #define DP_FEC_BS_JITTER_WA … #define PSR2_VSC_ENABLE_PROG_HEADER … #define DP_DSC_INSERT_SF_AT_EOL_WA … #define HDCP_LINE_REKEY_DISABLE … #define DISP_ARB_CTL … #define DISP_FBC_MEMORY_WAKE … #define DISP_TILE_SURFACE_SWIZZLING … #define DISP_FBC_WM_DIS … #define DISP_ARB_CTL2 … #define DISP_DATA_PARTITION_5_6 … #define DISP_IPC_ENABLE … #define GEN7_MSG_CTL … #define WAIT_FOR_PCH_RESET_ACK … #define WAIT_FOR_PCH_FLR_ACK … #define _BW_BUDDY0_CTL … #define _BW_BUDDY1_CTL … #define BW_BUDDY_CTL(x) … #define BW_BUDDY_DISABLE … #define BW_BUDDY_TLB_REQ_TIMER_MASK … #define BW_BUDDY_TLB_REQ_TIMER(x) … #define _BW_BUDDY0_PAGE_MASK … #define _BW_BUDDY1_PAGE_MASK … #define BW_BUDDY_PAGE_MASK(x) … #define HSW_NDE_RSTWRN_OPT … #define MTL_RESET_PICA_HANDSHAKE_EN … #define RESET_PCH_HANDSHAKE_ENABLE … #define GEN8_CHICKEN_DCPR_1 … #define LATENCY_REPORTING_REMOVED_PIPE_D … #define SKL_SELECT_ALTERNATE_DC_EXIT … #define LATENCY_REPORTING_REMOVED_PIPE_C … #define LATENCY_REPORTING_REMOVED_PIPE_B … #define LATENCY_REPORTING_REMOVED_PIPE_A … #define ICL_DELAY_PMRSP … #define DISABLE_FLR_SRC … #define MASK_WAKEMEM … #define DDI_CLOCK_REG_ACCESS … #define GEN11_CHICKEN_DCPR_2 … #define DCPR_MASK_MAXLATENCY_MEMUP_CLR … #define DCPR_MASK_LPMODE … #define DCPR_SEND_RESP_IMM … #define DCPR_CLEAR_MEMSTAT_DIS … #define XELPD_CHICKEN_DCPR_3 … #define DMD_RSP_TIMEOUT_DISABLE … #define SKL_DFSM … #define SKL_DFSM_DISPLAY_PM_DISABLE … #define SKL_DFSM_DISPLAY_HDCP_DISABLE … #define SKL_DFSM_CDCLK_LIMIT_MASK … #define SKL_DFSM_CDCLK_LIMIT_675 … #define SKL_DFSM_CDCLK_LIMIT_540 … #define SKL_DFSM_CDCLK_LIMIT_450 … #define SKL_DFSM_CDCLK_LIMIT_337_5 … #define ICL_DFSM_DMC_DISABLE … #define SKL_DFSM_PIPE_A_DISABLE … #define SKL_DFSM_PIPE_B_DISABLE … #define SKL_DFSM_PIPE_C_DISABLE … #define TGL_DFSM_PIPE_D_DISABLE … #define GLK_DFSM_DISPLAY_DSC_DISABLE … #define XE2LPD_DE_CAP … #define XE2LPD_DE_CAP_3DLUT_MASK … #define XE2LPD_DE_CAP_DSC_MASK … #define XE2LPD_DE_CAP_DSC_REMOVED … #define XE2LPD_DE_CAP_SCALER_MASK … #define XE2LPD_DE_CAP_SCALER_SINGLE … #define SKL_DSSM … #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK … #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz … #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz … #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz … #define GMD_ID_DISPLAY … #define GMD_ID_ARCH_MASK … #define GMD_ID_RELEASE_MASK … #define GMD_ID_STEP … /*GEN11 chicken */ #define _PIPEA_CHICKEN … #define _PIPEB_CHICKEN … #define _PIPEC_CHICKEN … #define PIPE_CHICKEN(pipe) … #define UNDERRUN_RECOVERY_DISABLE_ADLP … #define UNDERRUN_RECOVERY_ENABLE_DG2 … #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU … #define DG2_RENDER_CCSTAG_4_3_EN … #define PER_PIXEL_ALPHA_BYPASS_EN … /* PCH */ #define PCH_DISPLAY_BASE … /* south display engine interrupt: IBX */ #define SDE_AUDIO_POWER_D … #define SDE_AUDIO_POWER_C … #define SDE_AUDIO_POWER_B … #define SDE_AUDIO_POWER_SHIFT … #define SDE_AUDIO_POWER_MASK … #define SDE_GMBUS … #define SDE_AUDIO_HDCP_TRANSB … #define SDE_AUDIO_HDCP_TRANSA … #define SDE_AUDIO_HDCP_MASK … #define SDE_AUDIO_TRANSB … #define SDE_AUDIO_TRANSA … #define SDE_AUDIO_TRANS_MASK … #define SDE_POISON … /* 18 reserved */ #define SDE_FDI_RXB … #define SDE_FDI_RXA … #define SDE_FDI_MASK … #define SDE_AUXD … #define SDE_AUXC … #define SDE_AUXB … #define SDE_AUX_MASK … /* 12 reserved */ #define SDE_CRT_HOTPLUG … #define SDE_PORTD_HOTPLUG … #define SDE_PORTC_HOTPLUG … #define SDE_PORTB_HOTPLUG … #define SDE_SDVOB_HOTPLUG … #define SDE_HOTPLUG_MASK … #define SDE_TRANSB_CRC_DONE … #define SDE_TRANSB_CRC_ERR … #define SDE_TRANSB_FIFO_UNDER … #define SDE_TRANSA_CRC_DONE … #define SDE_TRANSA_CRC_ERR … #define SDE_TRANSA_FIFO_UNDER … #define SDE_TRANS_MASK … /* south display engine interrupt: CPT - CNP */ #define SDE_AUDIO_POWER_D_CPT … #define SDE_AUDIO_POWER_C_CPT … #define SDE_AUDIO_POWER_B_CPT … #define SDE_AUDIO_POWER_SHIFT_CPT … #define SDE_AUDIO_POWER_MASK_CPT … #define SDE_AUXD_CPT … #define SDE_AUXC_CPT … #define SDE_AUXB_CPT … #define SDE_AUX_MASK_CPT … #define SDE_PORTE_HOTPLUG_SPT … #define SDE_PORTA_HOTPLUG_SPT … #define SDE_PORTD_HOTPLUG_CPT … #define SDE_PORTC_HOTPLUG_CPT … #define SDE_PORTB_HOTPLUG_CPT … #define SDE_CRT_HOTPLUG_CPT … #define SDE_SDVOB_HOTPLUG_CPT … #define SDE_HOTPLUG_MASK_CPT … #define SDE_HOTPLUG_MASK_SPT … #define SDE_GMBUS_CPT … #define SDE_ERROR_CPT … #define SDE_AUDIO_CP_REQ_C_CPT … #define SDE_AUDIO_CP_CHG_C_CPT … #define SDE_FDI_RXC_CPT … #define SDE_AUDIO_CP_REQ_B_CPT … #define SDE_AUDIO_CP_CHG_B_CPT … #define SDE_FDI_RXB_CPT … #define SDE_AUDIO_CP_REQ_A_CPT … #define SDE_AUDIO_CP_CHG_A_CPT … #define SDE_FDI_RXA_CPT … #define SDE_AUDIO_CP_REQ_CPT … #define SDE_AUDIO_CP_CHG_CPT … #define SDE_FDI_MASK_CPT … /* south display engine interrupt: ICP/TGP/MTP */ #define SDE_PICAINTERRUPT … #define SDE_GMBUS_ICP … #define SDE_TC_HOTPLUG_ICP(hpd_pin) … #define SDE_TC_HOTPLUG_DG2(hpd_pin) … #define SDE_DDI_HOTPLUG_ICP(hpd_pin) … #define SDE_DDI_HOTPLUG_MASK_ICP … #define SDE_TC_HOTPLUG_MASK_ICP … #define SDEISR … #define SDEIMR … #define SDEIIR … #define SDEIER … #define SERR_INT … #define SERR_INT_POISON … #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) … /* digital port hotplug */ #define PCH_PORT_HOTPLUG … #define PORTA_HOTPLUG_ENABLE … #define BXT_DDIA_HPD_INVERT … #define PORTA_HOTPLUG_STATUS_MASK … #define PORTA_HOTPLUG_NO_DETECT … #define PORTA_HOTPLUG_SHORT_DETECT … #define PORTA_HOTPLUG_LONG_DETECT … #define PORTD_HOTPLUG_ENABLE … #define PORTD_PULSE_DURATION_2ms … #define PORTD_PULSE_DURATION_4_5ms … #define PORTD_PULSE_DURATION_6ms … #define PORTD_PULSE_DURATION_100ms … #define PORTD_PULSE_DURATION_MASK … #define PORTD_HOTPLUG_STATUS_MASK … #define PORTD_HOTPLUG_NO_DETECT … #define PORTD_HOTPLUG_SHORT_DETECT … #define PORTD_HOTPLUG_LONG_DETECT … #define PORTC_HOTPLUG_ENABLE … #define BXT_DDIC_HPD_INVERT … #define PORTC_PULSE_DURATION_2ms … #define PORTC_PULSE_DURATION_4_5ms … #define PORTC_PULSE_DURATION_6ms … #define PORTC_PULSE_DURATION_100ms … #define PORTC_PULSE_DURATION_MASK … #define PORTC_HOTPLUG_STATUS_MASK … #define PORTC_HOTPLUG_NO_DETECT … #define PORTC_HOTPLUG_SHORT_DETECT … #define PORTC_HOTPLUG_LONG_DETECT … #define PORTB_HOTPLUG_ENABLE … #define BXT_DDIB_HPD_INVERT … #define PORTB_PULSE_DURATION_2ms … #define PORTB_PULSE_DURATION_4_5ms … #define PORTB_PULSE_DURATION_6ms … #define PORTB_PULSE_DURATION_100ms … #define PORTB_PULSE_DURATION_MASK … #define PORTB_HOTPLUG_STATUS_MASK … #define PORTB_HOTPLUG_NO_DETECT … #define PORTB_HOTPLUG_SHORT_DETECT … #define PORTB_HOTPLUG_LONG_DETECT … #define BXT_DDI_HPD_INVERT_MASK … #define PCH_PORT_HOTPLUG2 … #define PORTE_HOTPLUG_ENABLE … #define PORTE_HOTPLUG_STATUS_MASK … #define PORTE_HOTPLUG_NO_DETECT … #define PORTE_HOTPLUG_SHORT_DETECT … #define PORTE_HOTPLUG_LONG_DETECT … /* This register is a reuse of PCH_PORT_HOTPLUG register. The * functionality covered in PCH_PORT_HOTPLUG is split into * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. */ #define SHOTPLUG_CTL_DDI … #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) … #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) … #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) … #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) … #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) … #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) … #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) … #define SHOTPLUG_CTL_TC … #define ICP_TC_HPD_ENABLE(hpd_pin) … #define ICP_TC_HPD_LONG_DETECT(hpd_pin) … #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) … #define SHPD_FILTER_CNT … #define SHPD_FILTER_CNT_500_ADJ … #define SHPD_FILTER_CNT_250 … #define _PCH_DPLL_A … #define _PCH_DPLL_B … #define PCH_DPLL(pll) … #define _PCH_FPA0 … #define FP_CB_TUNE … #define _PCH_FPA1 … #define _PCH_FPB0 … #define _PCH_FPB1 … #define PCH_FP0(pll) … #define PCH_FP1(pll) … #define PCH_DPLL_TEST … #define PCH_DREF_CONTROL … #define DREF_CONTROL_MASK … #define DREF_CPU_SOURCE_OUTPUT_DISABLE … #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD … #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD … #define DREF_CPU_SOURCE_OUTPUT_MASK … #define DREF_SSC_SOURCE_DISABLE … #define DREF_SSC_SOURCE_ENABLE … #define DREF_SSC_SOURCE_MASK … #define DREF_NONSPREAD_SOURCE_DISABLE … #define DREF_NONSPREAD_CK505_ENABLE … #define DREF_NONSPREAD_SOURCE_ENABLE … #define DREF_NONSPREAD_SOURCE_MASK … #define DREF_SUPERSPREAD_SOURCE_DISABLE … #define DREF_SUPERSPREAD_SOURCE_ENABLE … #define DREF_SUPERSPREAD_SOURCE_MASK … #define DREF_SSC4_DOWNSPREAD … #define DREF_SSC4_CENTERSPREAD … #define DREF_SSC1_DISABLE … #define DREF_SSC1_ENABLE … #define DREF_SSC4_DISABLE … #define DREF_SSC4_ENABLE … #define PCH_RAWCLK_FREQ … #define FDL_TP1_TIMER_SHIFT … #define FDL_TP1_TIMER_MASK … #define FDL_TP2_TIMER_SHIFT … #define FDL_TP2_TIMER_MASK … #define RAWCLK_FREQ_MASK … #define CNP_RAWCLK_DIV_MASK … #define CNP_RAWCLK_DIV(div) … #define CNP_RAWCLK_FRAC_MASK … #define CNP_RAWCLK_DEN(den) … #define ICP_RAWCLK_NUM(num) … #define PCH_DPLL_TMR_CFG … #define PCH_SSC4_PARMS … #define PCH_SSC4_AUX_PARMS … #define PCH_DPLL_SEL … #define TRANS_DPLLB_SEL(pipe) … #define TRANS_DPLLA_SEL(pipe) … #define TRANS_DPLL_ENABLE(pipe) … /* transcoder */ #define _PCH_TRANS_HTOTAL_A … #define TRANS_HTOTAL_SHIFT … #define TRANS_HACTIVE_SHIFT … #define _PCH_TRANS_HBLANK_A … #define TRANS_HBLANK_END_SHIFT … #define TRANS_HBLANK_START_SHIFT … #define _PCH_TRANS_HSYNC_A … #define TRANS_HSYNC_END_SHIFT … #define TRANS_HSYNC_START_SHIFT … #define _PCH_TRANS_VTOTAL_A … #define TRANS_VTOTAL_SHIFT … #define TRANS_VACTIVE_SHIFT … #define _PCH_TRANS_VBLANK_A … #define TRANS_VBLANK_END_SHIFT … #define TRANS_VBLANK_START_SHIFT … #define _PCH_TRANS_VSYNC_A … #define TRANS_VSYNC_END_SHIFT … #define TRANS_VSYNC_START_SHIFT … #define _PCH_TRANS_VSYNCSHIFT_A … #define _PCH_TRANSA_DATA_M1 … #define _PCH_TRANSA_DATA_N1 … #define _PCH_TRANSA_DATA_M2 … #define _PCH_TRANSA_DATA_N2 … #define _PCH_TRANSA_LINK_M1 … #define _PCH_TRANSA_LINK_N1 … #define _PCH_TRANSA_LINK_M2 … #define _PCH_TRANSA_LINK_N2 … /* Per-transcoder DIP controls (PCH) */ #define _VIDEO_DIP_CTL_A … #define _VIDEO_DIP_DATA_A … #define _VIDEO_DIP_GCP_A … #define GCP_COLOR_INDICATION … #define GCP_DEFAULT_PHASE_ENABLE … #define GCP_AV_MUTE … #define _VIDEO_DIP_CTL_B … #define _VIDEO_DIP_DATA_B … #define _VIDEO_DIP_GCP_B … #define TVIDEO_DIP_CTL(pipe) … #define TVIDEO_DIP_DATA(pipe) … #define TVIDEO_DIP_GCP(pipe) … /* Per-transcoder DIP controls (VLV) */ #define _VLV_VIDEO_DIP_CTL_A … #define _VLV_VIDEO_DIP_CTL_B … #define _CHV_VIDEO_DIP_CTL_C … #define VLV_TVIDEO_DIP_CTL(pipe) … #define _VLV_VIDEO_DIP_DATA_A … #define _VLV_VIDEO_DIP_DATA_B … #define _CHV_VIDEO_DIP_DATA_C … #define VLV_TVIDEO_DIP_DATA(pipe) … #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A … #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B … #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C … #define VLV_TVIDEO_DIP_GCP(pipe) … /* Haswell DIP controls */ #define _HSW_VIDEO_DIP_CTL_A … #define _HSW_VIDEO_DIP_AVI_DATA_A … #define _HSW_VIDEO_DIP_VS_DATA_A … #define _HSW_VIDEO_DIP_SPD_DATA_A … #define _HSW_VIDEO_DIP_GMP_DATA_A … #define _HSW_VIDEO_DIP_VSC_DATA_A … #define _ADL_VIDEO_DIP_AS_DATA_A … #define _GLK_VIDEO_DIP_DRM_DATA_A … #define _HSW_VIDEO_DIP_AVI_ECC_A … #define _HSW_VIDEO_DIP_VS_ECC_A … #define _HSW_VIDEO_DIP_SPD_ECC_A … #define _HSW_VIDEO_DIP_GMP_ECC_A … #define _HSW_VIDEO_DIP_VSC_ECC_A … #define _HSW_VIDEO_DIP_GCP_A … #define _HSW_VIDEO_DIP_CTL_B … #define _HSW_VIDEO_DIP_AVI_DATA_B … #define _HSW_VIDEO_DIP_VS_DATA_B … #define _HSW_VIDEO_DIP_SPD_DATA_B … #define _HSW_VIDEO_DIP_GMP_DATA_B … #define _HSW_VIDEO_DIP_VSC_DATA_B … #define _ADL_VIDEO_DIP_AS_DATA_B … #define _GLK_VIDEO_DIP_DRM_DATA_B … #define _HSW_VIDEO_DIP_BVI_ECC_B … #define _HSW_VIDEO_DIP_VS_ECC_B … #define _HSW_VIDEO_DIP_SPD_ECC_B … #define _HSW_VIDEO_DIP_GMP_ECC_B … #define _HSW_VIDEO_DIP_VSC_ECC_B … #define _HSW_VIDEO_DIP_GCP_B … /* Icelake PPS_DATA and _ECC DIP Registers. * These are available for transcoders B,C and eDP. * Adding the _A so as to reuse the _MMIO_TRANS2 * definition, with which it offsets to the right location. */ #define _ICL_VIDEO_DIP_PPS_DATA_A … #define _ICL_VIDEO_DIP_PPS_DATA_B … #define _ICL_VIDEO_DIP_PPS_ECC_A … #define _ICL_VIDEO_DIP_PPS_ECC_B … #define HSW_TVIDEO_DIP_CTL(dev_priv, trans) … #define HSW_TVIDEO_DIP_GCP(dev_priv, trans) … #define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) … #define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) … #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) … #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) … #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) … #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) … #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) … #define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) … /*ADLP and later: */ #define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) … #define _HSW_STEREO_3D_CTL_A … #define S3D_ENABLE … #define _HSW_STEREO_3D_CTL_B … #define HSW_STEREO_3D_CTL(dev_priv, trans) … #define _PCH_TRANS_HTOTAL_B … #define _PCH_TRANS_HBLANK_B … #define _PCH_TRANS_HSYNC_B … #define _PCH_TRANS_VTOTAL_B … #define _PCH_TRANS_VBLANK_B … #define _PCH_TRANS_VSYNC_B … #define _PCH_TRANS_VSYNCSHIFT_B … #define PCH_TRANS_HTOTAL(pipe) … #define PCH_TRANS_HBLANK(pipe) … #define PCH_TRANS_HSYNC(pipe) … #define PCH_TRANS_VTOTAL(pipe) … #define PCH_TRANS_VBLANK(pipe) … #define PCH_TRANS_VSYNC(pipe) … #define PCH_TRANS_VSYNCSHIFT(pipe) … #define _PCH_TRANSB_DATA_M1 … #define _PCH_TRANSB_DATA_N1 … #define _PCH_TRANSB_DATA_M2 … #define _PCH_TRANSB_DATA_N2 … #define _PCH_TRANSB_LINK_M1 … #define _PCH_TRANSB_LINK_N1 … #define _PCH_TRANSB_LINK_M2 … #define _PCH_TRANSB_LINK_N2 … #define PCH_TRANS_DATA_M1(pipe) … #define PCH_TRANS_DATA_N1(pipe) … #define PCH_TRANS_DATA_M2(pipe) … #define PCH_TRANS_DATA_N2(pipe) … #define PCH_TRANS_LINK_M1(pipe) … #define PCH_TRANS_LINK_N1(pipe) … #define PCH_TRANS_LINK_M2(pipe) … #define PCH_TRANS_LINK_N2(pipe) … #define _PCH_TRANSACONF … #define _PCH_TRANSBCONF … #define PCH_TRANSCONF(pipe) … #define LPT_TRANSCONF … #define TRANS_ENABLE … #define TRANS_STATE_ENABLE … #define TRANS_FRAME_START_DELAY_MASK … #define TRANS_FRAME_START_DELAY(x) … #define TRANS_INTERLACE_MASK … #define TRANS_INTERLACE_PROGRESSIVE … #define TRANS_INTERLACE_LEGACY_VSYNC_IBX … #define TRANS_INTERLACE_INTERLACED … #define TRANS_BPC_MASK … #define TRANS_BPC_8 … #define TRANS_BPC_10 … #define TRANS_BPC_6 … #define TRANS_BPC_12 … #define _TRANSA_CHICKEN1 … #define _TRANSB_CHICKEN1 … #define TRANS_CHICKEN1(pipe) … #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE … #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE … #define _TRANSA_CHICKEN2 … #define _TRANSB_CHICKEN2 … #define TRANS_CHICKEN2(pipe) … #define TRANS_CHICKEN2_TIMING_OVERRIDE … #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED … #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK … #define TRANS_CHICKEN2_FRAME_START_DELAY(x) … #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER … #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH … #define SOUTH_CHICKEN1 … #define FDIA_PHASE_SYNC_SHIFT_OVR … #define FDIA_PHASE_SYNC_SHIFT_EN … #define INVERT_DDIE_HPD … #define INVERT_DDID_HPD_MTP … #define INVERT_TC4_HPD … #define INVERT_TC3_HPD … #define INVERT_TC2_HPD … #define INVERT_TC1_HPD … #define INVERT_DDID_HPD … #define INVERT_DDIC_HPD … #define INVERT_DDIB_HPD … #define INVERT_DDIA_HPD … #define FDI_PHASE_SYNC_OVR(pipe) … #define FDI_PHASE_SYNC_EN(pipe) … #define FDI_BC_BIFURCATION_SELECT … #define CHASSIS_CLK_REQ_DURATION_MASK … #define CHASSIS_CLK_REQ_DURATION(x) … #define SBCLK_RUN_REFCLK_DIS … #define ICP_SECOND_PPS_IO_SELECT … #define SPT_PWM_GRANULARITY … #define SOUTH_CHICKEN2 … #define FDI_MPHY_IOSFSB_RESET_STATUS … #define FDI_MPHY_IOSFSB_RESET_CTL … #define LPT_PWM_GRANULARITY … #define DPLS_EDP_PPS_FIX_DIS … #define SOUTH_DSPCLK_GATE_D … #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE … #define PCH_DPLUNIT_CLOCK_GATE_DISABLE … #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE … #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE … #define PCH_CPUNIT_CLOCK_GATE_DISABLE … #define CNP_PWM_CGE_GATING_DISABLE … #define PCH_LP_PARTITION_LEVEL_DISABLE … #define PCH_DP_B … #define PCH_DP_C … #define PCH_DP_D … /* CPT */ #define _TRANS_DP_CTL_A … #define _TRANS_DP_CTL_B … #define _TRANS_DP_CTL_C … #define TRANS_DP_CTL(pipe) … #define TRANS_DP_OUTPUT_ENABLE … #define TRANS_DP_PORT_SEL_MASK … #define TRANS_DP_PORT_SEL_NONE … #define TRANS_DP_PORT_SEL(port) … #define TRANS_DP_AUDIO_ONLY … #define TRANS_DP_ENH_FRAMING … #define TRANS_DP_BPC_MASK … #define TRANS_DP_BPC_8 … #define TRANS_DP_BPC_10 … #define TRANS_DP_BPC_6 … #define TRANS_DP_BPC_12 … #define TRANS_DP_VSYNC_ACTIVE_HIGH … #define TRANS_DP_HSYNC_ACTIVE_HIGH … #define _TRANS_DP2_CTL_A … #define _TRANS_DP2_CTL_B … #define _TRANS_DP2_CTL_C … #define _TRANS_DP2_CTL_D … #define TRANS_DP2_CTL(trans) … #define TRANS_DP2_128B132B_CHANNEL_CODING … #define TRANS_DP2_PANEL_REPLAY_ENABLE … #define TRANS_DP2_DEBUG_ENABLE … #define _TRANS_DP2_VFREQHIGH_A … #define _TRANS_DP2_VFREQHIGH_B … #define _TRANS_DP2_VFREQHIGH_C … #define _TRANS_DP2_VFREQHIGH_D … #define TRANS_DP2_VFREQHIGH(trans) … #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK … #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) … #define _TRANS_DP2_VFREQLOW_A … #define _TRANS_DP2_VFREQLOW_B … #define _TRANS_DP2_VFREQLOW_C … #define _TRANS_DP2_VFREQLOW_D … #define TRANS_DP2_VFREQLOW(trans) … /* SNB eDP training params */ /* SNB A-stepping */ #define EDP_LINK_TRAIN_400MV_0DB_SNB_A … #define EDP_LINK_TRAIN_400MV_6DB_SNB_A … #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A … #define EDP_LINK_TRAIN_800MV_0DB_SNB_A … /* SNB B-stepping */ #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B … #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B … #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B … #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B … #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B … #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB … /* IVB */ #define EDP_LINK_TRAIN_400MV_0DB_IVB … #define EDP_LINK_TRAIN_400MV_3_5DB_IVB … #define EDP_LINK_TRAIN_400MV_6DB_IVB … #define EDP_LINK_TRAIN_600MV_0DB_IVB … #define EDP_LINK_TRAIN_600MV_3_5DB_IVB … #define EDP_LINK_TRAIN_800MV_0DB_IVB … #define EDP_LINK_TRAIN_800MV_3_5DB_IVB … /* legacy values */ #define EDP_LINK_TRAIN_500MV_0DB_IVB … #define EDP_LINK_TRAIN_1000MV_0DB_IVB … #define EDP_LINK_TRAIN_500MV_3_5DB_IVB … #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB … #define EDP_LINK_TRAIN_1000MV_6DB_IVB … #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB … #define VLV_PMWGICZ … #define HSW_EDRAM_CAP … #define EDRAM_ENABLED … #define EDRAM_NUM_BANKS(cap) … #define EDRAM_WAYS_IDX(cap) … #define EDRAM_SETS_IDX(cap) … #define VLV_CHICKEN_3 … #define PIXEL_OVERLAP_CNT_MASK … #define PIXEL_OVERLAP_CNT_SHIFT … #define GEN6_PCODE_MAILBOX … #define GEN6_PCODE_READY … #define GEN6_PCODE_MB_PARAM2 … #define GEN6_PCODE_MB_PARAM1 … #define GEN6_PCODE_MB_COMMAND … #define GEN6_PCODE_ERROR_MASK … #define GEN6_PCODE_SUCCESS … #define GEN6_PCODE_ILLEGAL_CMD … #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE … #define GEN6_PCODE_TIMEOUT … #define GEN6_PCODE_UNIMPLEMENTED_CMD … #define GEN7_PCODE_TIMEOUT … #define GEN7_PCODE_ILLEGAL_DATA … #define GEN11_PCODE_ILLEGAL_SUBCOMMAND … #define GEN11_PCODE_LOCKED … #define GEN11_PCODE_REJECTED … #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE … #define GEN6_PCODE_WRITE_RC6VIDS … #define GEN6_PCODE_READ_RC6VIDS … #define GEN6_ENCODE_RC6_VID(mv) … #define GEN6_DECODE_RC6_VID(vids) … #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ … #define GEN9_PCODE_READ_MEM_LATENCY … #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK … #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK … #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK … #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK … #define SKL_PCODE_LOAD_HDCP_KEYS … #define SKL_PCODE_CDCLK_CONTROL … #define SKL_CDCLK_PREPARE_FOR_CHANGE … #define SKL_CDCLK_READY_FOR_CHANGE … #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE … #define GEN6_PCODE_READ_MIN_FREQ_TABLE … #define GEN6_READ_OC_PARAMS … #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO … #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO … #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) … #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO … #define DISPLAY_TO_PCODE_CDCLK_MAX … #define DISPLAY_TO_PCODE_VOLTAGE_MASK … #define DISPLAY_TO_PCODE_VOLTAGE_MAX … #define DISPLAY_TO_PCODE_CDCLK_VALID … #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID … #define DISPLAY_TO_PCODE_CDCLK_MASK … #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK … #define DISPLAY_TO_PCODE_CDCLK(x) … #define DISPLAY_TO_PCODE_PIPE_COUNT(x) … #define DISPLAY_TO_PCODE_VOLTAGE(x) … #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) … #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG … #define ICL_PCODE_REP_QGV_MASK … #define ICL_PCODE_REP_QGV_SAFE … #define ICL_PCODE_REP_QGV_POLL … #define ICL_PCODE_REP_QGV_REJECTED … #define ADLS_PCODE_REP_PSF_MASK … #define ADLS_PCODE_REP_PSF_SAFE … #define ADLS_PCODE_REP_PSF_POLL … #define ADLS_PCODE_REP_PSF_REJECTED … #define ICL_PCODE_REQ_QGV_PT_MASK … #define ICL_PCODE_REQ_QGV_PT(x) … #define ADLS_PCODE_REQ_PSF_PT_MASK … #define ADLS_PCODE_REQ_PSF_PT(x) … #define GEN6_PCODE_READ_D_COMP … #define GEN6_PCODE_WRITE_D_COMP … #define ICL_PCODE_EXIT_TCCOLD … #define HSW_PCODE_DE_WRITE_FREQ_REQ … #define DISPLAY_IPS_CONTROL … #define TGL_PCODE_TCCOLD … #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED … #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ … #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ … /* See also IPS_CTL */ #define IPS_PCODE_CONTROL … #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL … #define GEN9_PCODE_SAGV_CONTROL … #define GEN9_SAGV_DISABLE … #define GEN9_SAGV_IS_DISABLED … #define GEN9_SAGV_ENABLE … #define DG1_PCODE_STATUS … #define DG1_UNCORE_GET_INIT_STATUS … #define DG1_UNCORE_INIT_STATUS_COMPLETE … #define PCODE_POWER_SETUP … #define POWER_SETUP_SUBCOMMAND_READ_I1 … #define POWER_SETUP_SUBCOMMAND_WRITE_I1 … #define POWER_SETUP_I1_WATTS … #define POWER_SETUP_I1_SHIFT … #define POWER_SETUP_I1_DATA_MASK … #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US … #define XEHP_PCODE_FREQUENCY_CONFIG … /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ #define PCODE_MBOX_FC_SC_READ_FUSED_P0 … #define PCODE_MBOX_FC_SC_READ_FUSED_PN … /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ #define PCODE_MBOX_DOMAIN_NONE … #define PCODE_MBOX_DOMAIN_MEDIAFF … #define GEN6_PCODE_DATA … #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT … #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT … #define GEN6_PCODE_DATA1 … #define MTL_PCODE_STOLEN_ACCESS … #define STOLEN_ACCESS_ALLOWED … /* IVYBRIDGE DPF */ #define GEN7_L3CDERRST1(slice) … #define GEN7_L3CDERRST1_ROW_MASK … #define GEN7_PARITY_ERROR_VALID … #define GEN7_L3CDERRST1_BANK_MASK … #define GEN7_L3CDERRST1_SUBBANK_MASK … #define GEN7_PARITY_ERROR_ROW(reg) … #define GEN7_PARITY_ERROR_BANK(reg) … #define GEN7_PARITY_ERROR_SUBBANK(reg) … #define GEN7_L3CDERRST1_ENABLE … /* These are the 4 32-bit write offset registers for each stream * output buffer. It determines the offset from the * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. */ #define GEN7_SO_WRITE_OFFSET(n) … /* * HSW - ICL power wells * * Platforms have up to 3 power well control register sets, each set * controlling up to 16 power wells via a request/status HW flag tuple: * - main (HSW_PWR_WELL_CTL[1-4]) * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) * Each control register set consists of up to 4 registers used by different * sources that can request a power well to be enabled: * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) */ #define HSW_PWR_WELL_CTL1 … #define HSW_PWR_WELL_CTL2 … #define HSW_PWR_WELL_CTL3 … #define HSW_PWR_WELL_CTL4 … #define HSW_PWR_WELL_CTL_REQ(pw_idx) … #define HSW_PWR_WELL_CTL_STATE(pw_idx) … /* HSW/BDW power well */ #define HSW_PW_CTL_IDX_GLOBAL … /* SKL/BXT/GLK power wells */ #define SKL_PW_CTL_IDX_PW_2 … #define SKL_PW_CTL_IDX_PW_1 … #define GLK_PW_CTL_IDX_AUX_C … #define GLK_PW_CTL_IDX_AUX_B … #define GLK_PW_CTL_IDX_AUX_A … #define SKL_PW_CTL_IDX_DDI_D … #define SKL_PW_CTL_IDX_DDI_C … #define SKL_PW_CTL_IDX_DDI_B … #define SKL_PW_CTL_IDX_DDI_A_E … #define GLK_PW_CTL_IDX_DDI_A … #define SKL_PW_CTL_IDX_MISC_IO … /* ICL/TGL - power wells */ #define TGL_PW_CTL_IDX_PW_5 … #define ICL_PW_CTL_IDX_PW_4 … #define ICL_PW_CTL_IDX_PW_3 … #define ICL_PW_CTL_IDX_PW_2 … #define ICL_PW_CTL_IDX_PW_1 … /* XE_LPD - power wells */ #define XELPD_PW_CTL_IDX_PW_D … #define XELPD_PW_CTL_IDX_PW_C … #define XELPD_PW_CTL_IDX_PW_B … #define XELPD_PW_CTL_IDX_PW_A … #define ICL_PWR_WELL_CTL_AUX1 … #define ICL_PWR_WELL_CTL_AUX2 … #define ICL_PWR_WELL_CTL_AUX4 … #define TGL_PW_CTL_IDX_AUX_TBT6 … #define TGL_PW_CTL_IDX_AUX_TBT5 … #define TGL_PW_CTL_IDX_AUX_TBT4 … #define ICL_PW_CTL_IDX_AUX_TBT4 … #define TGL_PW_CTL_IDX_AUX_TBT3 … #define ICL_PW_CTL_IDX_AUX_TBT3 … #define TGL_PW_CTL_IDX_AUX_TBT2 … #define ICL_PW_CTL_IDX_AUX_TBT2 … #define TGL_PW_CTL_IDX_AUX_TBT1 … #define ICL_PW_CTL_IDX_AUX_TBT1 … #define TGL_PW_CTL_IDX_AUX_TC6 … #define XELPD_PW_CTL_IDX_AUX_E … #define TGL_PW_CTL_IDX_AUX_TC5 … #define XELPD_PW_CTL_IDX_AUX_D … #define TGL_PW_CTL_IDX_AUX_TC4 … #define ICL_PW_CTL_IDX_AUX_F … #define TGL_PW_CTL_IDX_AUX_TC3 … #define ICL_PW_CTL_IDX_AUX_E … #define TGL_PW_CTL_IDX_AUX_TC2 … #define ICL_PW_CTL_IDX_AUX_D … #define TGL_PW_CTL_IDX_AUX_TC1 … #define ICL_PW_CTL_IDX_AUX_C … #define ICL_PW_CTL_IDX_AUX_B … #define ICL_PW_CTL_IDX_AUX_A … #define ICL_PWR_WELL_CTL_DDI1 … #define ICL_PWR_WELL_CTL_DDI2 … #define ICL_PWR_WELL_CTL_DDI4 … #define XELPD_PW_CTL_IDX_DDI_E … #define TGL_PW_CTL_IDX_DDI_TC6 … #define XELPD_PW_CTL_IDX_DDI_D … #define TGL_PW_CTL_IDX_DDI_TC5 … #define TGL_PW_CTL_IDX_DDI_TC4 … #define ICL_PW_CTL_IDX_DDI_F … #define TGL_PW_CTL_IDX_DDI_TC3 … #define ICL_PW_CTL_IDX_DDI_E … #define TGL_PW_CTL_IDX_DDI_TC2 … #define ICL_PW_CTL_IDX_DDI_D … #define TGL_PW_CTL_IDX_DDI_TC1 … #define ICL_PW_CTL_IDX_DDI_C … #define ICL_PW_CTL_IDX_DDI_B … #define ICL_PW_CTL_IDX_DDI_A … /* HSW - power well misc debug registers */ #define HSW_PWR_WELL_CTL5 … #define HSW_PWR_WELL_ENABLE_SINGLE_STEP … #define HSW_PWR_WELL_PWR_GATE_OVERRIDE … #define HSW_PWR_WELL_FORCE_ON … #define HSW_PWR_WELL_CTL6 … /* SKL Fuse Status */ enum skl_power_gate { … }; #define SKL_FUSE_STATUS … #define SKL_FUSE_DOWNLOAD_STATUS … /* * PG0 is HW controlled, so doesn't have a corresponding power well control knob * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 */ #define SKL_PW_CTL_IDX_TO_PG(pw_idx) … /* * PG0 is HW controlled, so doesn't have a corresponding power well control knob * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 */ #define ICL_PW_CTL_IDX_TO_PG(pw_idx) … #define SKL_FUSE_PG_DIST_STATUS(pg) … /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A … #define _TRANS_DDI_FUNC_CTL_B … #define _TRANS_DDI_FUNC_CTL_C … #define _TRANS_DDI_FUNC_CTL_D … #define _TRANS_DDI_FUNC_CTL_EDP … #define _TRANS_DDI_FUNC_CTL_DSI0 … #define _TRANS_DDI_FUNC_CTL_DSI1 … #define TRANS_DDI_FUNC_CTL(dev_priv, tran) … #define TRANS_DDI_FUNC_ENABLE … /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ #define TRANS_DDI_PORT_SHIFT … #define TGL_TRANS_DDI_PORT_SHIFT … #define TRANS_DDI_PORT_MASK … #define TGL_TRANS_DDI_PORT_MASK … #define TRANS_DDI_SELECT_PORT(x) … #define TGL_TRANS_DDI_SELECT_PORT(x) … #define TRANS_DDI_MODE_SELECT_MASK … #define TRANS_DDI_MODE_SELECT_HDMI … #define TRANS_DDI_MODE_SELECT_DVI … #define TRANS_DDI_MODE_SELECT_DP_SST … #define TRANS_DDI_MODE_SELECT_DP_MST … #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B … #define TRANS_DDI_BPC_MASK … #define TRANS_DDI_BPC_8 … #define TRANS_DDI_BPC_10 … #define TRANS_DDI_BPC_6 … #define TRANS_DDI_BPC_12 … #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK … #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) … #define TRANS_DDI_PVSYNC … #define TRANS_DDI_PHSYNC … #define TRANS_DDI_PORT_SYNC_ENABLE … #define TRANS_DDI_EDP_INPUT_MASK … #define TRANS_DDI_EDP_INPUT_A_ON … #define TRANS_DDI_EDP_INPUT_A_ONOFF … #define TRANS_DDI_EDP_INPUT_B_ONOFF … #define TRANS_DDI_EDP_INPUT_C_ONOFF … #define TRANS_DDI_EDP_INPUT_D_ONOFF … #define TRANS_DDI_HDCP_LINE_REKEY_DISABLE … #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK … #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) … #define TRANS_DDI_HDCP_SIGNALLING … #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC … #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE … #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ … #define TRANS_DDI_HDCP_SELECT … #define TRANS_DDI_BFI_ENABLE … #define TRANS_DDI_HIGH_TMDS_CHAR_RATE … #define TRANS_DDI_PORT_WIDTH_MASK … #define TRANS_DDI_PORT_WIDTH(width) … #define TRANS_DDI_HDMI_SCRAMBLING … #define TRANS_DDI_HDMI_SCRAMBLING_MASK … #define _TRANS_DDI_FUNC_CTL2_A … #define _TRANS_DDI_FUNC_CTL2_B … #define _TRANS_DDI_FUNC_CTL2_C … #define _TRANS_DDI_FUNC_CTL2_EDP … #define _TRANS_DDI_FUNC_CTL2_DSI0 … #define _TRANS_DDI_FUNC_CTL2_DSI1 … #define TRANS_DDI_FUNC_CTL2(dev_priv, tran) … #define PORT_SYNC_MODE_ENABLE … #define PORT_SYNC_MODE_MASTER_SELECT_MASK … #define PORT_SYNC_MODE_MASTER_SELECT(x) … #define TRANS_CMTG_CHICKEN … #define DISABLE_DPT_CLK_GATING … /* DisplayPort Transport Control */ #define _DP_TP_CTL_A … #define _DP_TP_CTL_B … #define _TGL_DP_TP_CTL_A … #define DP_TP_CTL(port) … #define TGL_DP_TP_CTL(dev_priv, tran) … #define DP_TP_CTL_ENABLE … #define DP_TP_CTL_FEC_ENABLE … #define DP_TP_CTL_MODE_SST … #define DP_TP_CTL_MODE_MST … #define DP_TP_CTL_FORCE_ACT … #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK … #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A … #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B … #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C … #define DP_TP_CTL_ENHANCED_FRAME_ENABLE … #define DP_TP_CTL_FDI_AUTOTRAIN … #define DP_TP_CTL_LINK_TRAIN_MASK … #define DP_TP_CTL_LINK_TRAIN_PAT1 … #define DP_TP_CTL_LINK_TRAIN_PAT2 … #define DP_TP_CTL_LINK_TRAIN_PAT3 … #define DP_TP_CTL_LINK_TRAIN_PAT4 … #define DP_TP_CTL_LINK_TRAIN_IDLE … #define DP_TP_CTL_LINK_TRAIN_NORMAL … #define DP_TP_CTL_SCRAMBLE_DISABLE … /* DisplayPort Transport Status */ #define _DP_TP_STATUS_A … #define _DP_TP_STATUS_B … #define _TGL_DP_TP_STATUS_A … #define DP_TP_STATUS(port) … #define TGL_DP_TP_STATUS(dev_priv, tran) … #define DP_TP_STATUS_FEC_ENABLE_LIVE … #define DP_TP_STATUS_IDLE_DONE … #define DP_TP_STATUS_ACT_SENT … #define DP_TP_STATUS_MODE_STATUS_MST … #define DP_TP_STATUS_AUTOTRAIN_DONE … #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 … #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 … #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 … /* DDI Buffer Control */ #define _DDI_BUF_CTL_A … #define _DDI_BUF_CTL_B … /* Known as DDI_CTL_DE in MTL+ */ #define DDI_BUF_CTL(port) … #define DDI_BUF_CTL_ENABLE … #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE … #define XE2LPD_DDI_BUF_D2D_LINK_STATE … #define DDI_BUF_TRANS_SELECT(n) … #define DDI_BUF_EMP_MASK … #define DDI_BUF_PHY_LINK_RATE(r) … #define DDI_BUF_PORT_DATA_MASK … #define DDI_BUF_PORT_DATA_10BIT … #define DDI_BUF_PORT_DATA_20BIT … #define DDI_BUF_PORT_DATA_40BIT … #define DDI_BUF_PORT_REVERSAL … #define DDI_BUF_IS_IDLE … #define DDI_BUF_CTL_TC_PHY_OWNERSHIP … #define DDI_A_4_LANES … #define DDI_PORT_WIDTH(width) … #define DDI_PORT_WIDTH_MASK … #define DDI_PORT_WIDTH_SHIFT … #define DDI_INIT_DISPLAY_DETECTED … /* DDI Buffer Translations */ #define _DDI_BUF_TRANS_A … #define _DDI_BUF_TRANS_B … #define DDI_BUF_TRANS_LO(port, i) … #define DDI_BUF_BALANCE_LEG_ENABLE … #define DDI_BUF_TRANS_HI(port, i) … /* DDI DP Compliance Control */ #define _DDI_DP_COMP_CTL_A … #define _DDI_DP_COMP_CTL_B … #define DDI_DP_COMP_CTL(pipe) … #define DDI_DP_COMP_CTL_ENABLE … #define DDI_DP_COMP_CTL_D10_2 … #define DDI_DP_COMP_CTL_SCRAMBLED_0 … #define DDI_DP_COMP_CTL_PRBS7 … #define DDI_DP_COMP_CTL_CUSTOM80 … #define DDI_DP_COMP_CTL_HBR2 … #define DDI_DP_COMP_CTL_SCRAMBLED_1 … #define DDI_DP_COMP_CTL_HBR2_RESET … /* DDI DP Compliance Pattern */ #define _DDI_DP_COMP_PAT_A … #define _DDI_DP_COMP_PAT_B … #define DDI_DP_COMP_PAT(pipe, i) … /* Sideband Interface (SBI) is programmed indirectly, via * SBI_ADDR, which contains the register offset; and SBI_DATA, * which contains the payload */ #define SBI_ADDR … #define SBI_DATA … #define SBI_CTL_STAT … #define SBI_CTL_DEST_ICLK … #define SBI_CTL_DEST_MPHY … #define SBI_CTL_OP_IORD … #define SBI_CTL_OP_IOWR … #define SBI_CTL_OP_CRRD … #define SBI_CTL_OP_CRWR … #define SBI_RESPONSE_FAIL … #define SBI_RESPONSE_SUCCESS … #define SBI_BUSY … #define SBI_READY … /* SBI offsets */ #define SBI_SSCDIVINTPHASE … #define SBI_SSCDIVINTPHASE6 … #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT … #define SBI_SSCDIVINTPHASE_DIVSEL_MASK … #define SBI_SSCDIVINTPHASE_DIVSEL(x) … #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT … #define SBI_SSCDIVINTPHASE_INCVAL_MASK … #define SBI_SSCDIVINTPHASE_INCVAL(x) … #define SBI_SSCDIVINTPHASE_DIR(x) … #define SBI_SSCDIVINTPHASE_PROPAGATE … #define SBI_SSCDITHPHASE … #define SBI_SSCCTL … #define SBI_SSCCTL6 … #define SBI_SSCCTL_PATHALT … #define SBI_SSCCTL_DISABLE … #define SBI_SSCAUXDIV6 … #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT … #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK … #define SBI_SSCAUXDIV_FINALDIV2SEL(x) … #define SBI_DBUFF0 … #define SBI_GEN0 … #define SBI_GEN0_CFG_BUFFENABLE_DISABLE … /* LPT PIXCLK_GATE */ #define PIXCLK_GATE … #define PIXCLK_GATE_UNGATE … #define PIXCLK_GATE_GATE … /* SPLL */ #define SPLL_CTL … #define SPLL_PLL_ENABLE … #define SPLL_REF_BCLK … #define SPLL_REF_MUXED_SSC … #define SPLL_REF_NON_SSC_HSW … #define SPLL_REF_PCH_SSC_BDW … #define SPLL_REF_LCPLL … #define SPLL_REF_MASK … #define SPLL_FREQ_810MHz … #define SPLL_FREQ_1350MHz … #define SPLL_FREQ_2700MHz … #define SPLL_FREQ_MASK … /* WRPLL */ #define _WRPLL_CTL1 … #define _WRPLL_CTL2 … #define WRPLL_CTL(pll) … #define WRPLL_PLL_ENABLE … #define WRPLL_REF_BCLK … #define WRPLL_REF_PCH_SSC … #define WRPLL_REF_MUXED_SSC_BDW … #define WRPLL_REF_SPECIAL_HSW … #define WRPLL_REF_LCPLL … #define WRPLL_REF_MASK … /* WRPLL divider programming */ #define WRPLL_DIVIDER_REFERENCE(x) … #define WRPLL_DIVIDER_REF_MASK … #define WRPLL_DIVIDER_POST(x) … #define WRPLL_DIVIDER_POST_MASK … #define WRPLL_DIVIDER_POST_SHIFT … #define WRPLL_DIVIDER_FEEDBACK(x) … #define WRPLL_DIVIDER_FB_SHIFT … #define WRPLL_DIVIDER_FB_MASK … /* Port clock selection */ #define _PORT_CLK_SEL_A … #define _PORT_CLK_SEL_B … #define PORT_CLK_SEL(port) … #define PORT_CLK_SEL_MASK … #define PORT_CLK_SEL_LCPLL_2700 … #define PORT_CLK_SEL_LCPLL_1350 … #define PORT_CLK_SEL_LCPLL_810 … #define PORT_CLK_SEL_SPLL … #define PORT_CLK_SEL_WRPLL(pll) … #define PORT_CLK_SEL_WRPLL1 … #define PORT_CLK_SEL_WRPLL2 … #define PORT_CLK_SEL_NONE … /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ #define DDI_CLK_SEL(port) … #define DDI_CLK_SEL_MASK … #define DDI_CLK_SEL_NONE … #define DDI_CLK_SEL_MG … #define DDI_CLK_SEL_TBT_162 … #define DDI_CLK_SEL_TBT_270 … #define DDI_CLK_SEL_TBT_540 … #define DDI_CLK_SEL_TBT_810 … /* Transcoder clock selection */ #define _TRANS_CLK_SEL_A … #define _TRANS_CLK_SEL_B … #define TRANS_CLK_SEL(tran) … /* For each transcoder, we need to select the corresponding port clock */ #define TRANS_CLK_SEL_DISABLED … #define TRANS_CLK_SEL_PORT(x) … #define TGL_TRANS_CLK_SEL_DISABLED … #define TGL_TRANS_CLK_SEL_PORT(x) … #define CDCLK_FREQ … #define _TRANSA_MSA_MISC … #define _TRANSB_MSA_MISC … #define _TRANSC_MSA_MISC … #define _TRANS_EDP_MSA_MISC … #define TRANS_MSA_MISC(dev_priv, tran) … /* See DP_MSA_MISC_* for the bit definitions */ #define _TRANS_A_SET_CONTEXT_LATENCY … #define _TRANS_B_SET_CONTEXT_LATENCY … #define _TRANS_C_SET_CONTEXT_LATENCY … #define _TRANS_D_SET_CONTEXT_LATENCY … #define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) … #define TRANS_SET_CONTEXT_LATENCY_MASK … #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) … /* LCPLL Control */ #define LCPLL_CTL … #define LCPLL_PLL_DISABLE … #define LCPLL_PLL_LOCK … #define LCPLL_REF_NON_SSC … #define LCPLL_REF_BCLK … #define LCPLL_REF_PCH_SSC … #define LCPLL_REF_MASK … #define LCPLL_CLK_FREQ_MASK … #define LCPLL_CLK_FREQ_450 … #define LCPLL_CLK_FREQ_54O_BDW … #define LCPLL_CLK_FREQ_337_5_BDW … #define LCPLL_CLK_FREQ_675_BDW … #define LCPLL_CD_CLOCK_DISABLE … #define LCPLL_ROOT_CD_CLOCK_DISABLE … #define LCPLL_CD2X_CLOCK_DISABLE … #define LCPLL_POWER_DOWN_ALLOW … #define LCPLL_CD_SOURCE_FCLK … #define LCPLL_CD_SOURCE_FCLK_DONE … /* * SKL Clocks */ /* CDCLK_CTL */ #define CDCLK_CTL … #define CDCLK_FREQ_SEL_MASK … #define CDCLK_FREQ_450_432 … #define CDCLK_FREQ_540 … #define CDCLK_FREQ_337_308 … #define CDCLK_FREQ_675_617 … #define MDCLK_SOURCE_SEL_MASK … #define MDCLK_SOURCE_SEL_CD2XCLK … #define MDCLK_SOURCE_SEL_CDCLK_PLL … #define BXT_CDCLK_CD2X_DIV_SEL_MASK … #define BXT_CDCLK_CD2X_DIV_SEL_1 … #define BXT_CDCLK_CD2X_DIV_SEL_1_5 … #define BXT_CDCLK_CD2X_DIV_SEL_2 … #define BXT_CDCLK_CD2X_DIV_SEL_4 … #define BXT_CDCLK_CD2X_PIPE(pipe) … #define CDCLK_DIVMUX_CD_OVERRIDE … #define BXT_CDCLK_CD2X_PIPE_NONE … #define ICL_CDCLK_CD2X_PIPE(pipe) … #define ICL_CDCLK_CD2X_PIPE_NONE … #define TGL_CDCLK_CD2X_PIPE(pipe) … #define TGL_CDCLK_CD2X_PIPE_NONE … #define BXT_CDCLK_SSA_PRECHARGE_ENABLE … #define CDCLK_FREQ_DECIMAL_MASK … /* CDCLK_SQUASH_CTL */ #define CDCLK_SQUASH_CTL … #define CDCLK_SQUASH_ENABLE … #define CDCLK_SQUASH_WINDOW_SIZE_MASK … #define CDCLK_SQUASH_WINDOW_SIZE(x) … #define CDCLK_SQUASH_WAVEFORM_MASK … #define CDCLK_SQUASH_WAVEFORM(x) … /* LCPLL_CTL */ #define LCPLL1_CTL … #define LCPLL2_CTL … #define LCPLL_PLL_ENABLE … /* DPLL control1 */ #define DPLL_CTRL1 … #define DPLL_CTRL1_HDMI_MODE(id) … #define DPLL_CTRL1_SSC(id) … #define DPLL_CTRL1_LINK_RATE_MASK(id) … #define DPLL_CTRL1_LINK_RATE_SHIFT(id) … #define DPLL_CTRL1_LINK_RATE(linkrate, id) … #define DPLL_CTRL1_OVERRIDE(id) … #define DPLL_CTRL1_LINK_RATE_2700 … #define DPLL_CTRL1_LINK_RATE_1350 … #define DPLL_CTRL1_LINK_RATE_810 … #define DPLL_CTRL1_LINK_RATE_1620 … #define DPLL_CTRL1_LINK_RATE_1080 … #define DPLL_CTRL1_LINK_RATE_2160 … /* DPLL control2 */ #define DPLL_CTRL2 … #define DPLL_CTRL2_DDI_CLK_OFF(port) … #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) … #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) … #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) … #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) … /* DPLL Status */ #define DPLL_STATUS … #define DPLL_LOCK(id) … /* DPLL cfg */ #define _DPLL1_CFGCR1 … #define _DPLL2_CFGCR1 … #define _DPLL3_CFGCR1 … #define DPLL_CFGCR1_FREQ_ENABLE … #define DPLL_CFGCR1_DCO_FRACTION_MASK … #define DPLL_CFGCR1_DCO_FRACTION(x) … #define DPLL_CFGCR1_DCO_INTEGER_MASK … #define _DPLL1_CFGCR2 … #define _DPLL2_CFGCR2 … #define _DPLL3_CFGCR2 … #define DPLL_CFGCR2_QDIV_RATIO_MASK … #define DPLL_CFGCR2_QDIV_RATIO(x) … #define DPLL_CFGCR2_QDIV_MODE(x) … #define DPLL_CFGCR2_KDIV_MASK … #define DPLL_CFGCR2_KDIV(x) … #define DPLL_CFGCR2_KDIV_5 … #define DPLL_CFGCR2_KDIV_2 … #define DPLL_CFGCR2_KDIV_3 … #define DPLL_CFGCR2_KDIV_1 … #define DPLL_CFGCR2_PDIV_MASK … #define DPLL_CFGCR2_PDIV(x) … #define DPLL_CFGCR2_PDIV_1 … #define DPLL_CFGCR2_PDIV_2 … #define DPLL_CFGCR2_PDIV_3 … #define DPLL_CFGCR2_PDIV_7 … #define DPLL_CFGCR2_PDIV_7_INVALID … #define DPLL_CFGCR2_CENTRAL_FREQ_MASK … #define DPLL_CFGCR1(id) … #define DPLL_CFGCR2(id) … /* ICL Clocks */ #define ICL_DPCLKA_CFGCR0 … #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) … #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) … #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) … #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) … #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) … #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) … #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) … #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) … #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) … /* * DG1 Clocks * First registers controls the first A and B, while the second register * controls the phy C and D. The bits on these registers are the * same, but refer to different phys */ #define _DG1_DPCLKA_CFGCR0 … #define _DG1_DPCLKA1_CFGCR0 … #define _DG1_DPCLKA_PHY_IDX(phy) … #define _DG1_DPCLKA_PLL_IDX(pll) … #define DG1_DPCLKA_CFGCR0(phy) … #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) … #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) … #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) … #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) … /* ADLS Clocks */ #define _ADLS_DPCLKA_CFGCR0 … #define _ADLS_DPCLKA_CFGCR1 … #define ADLS_DPCLKA_CFGCR(phy) … #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) … /* ADLS DPCLKA_CFGCR0 DDI mask */ #define ADLS_DPCLKA_DDII_SEL_MASK … #define ADLS_DPCLKA_DDIB_SEL_MASK … #define ADLS_DPCLKA_DDIA_SEL_MASK … /* ADLS DPCLKA_CFGCR1 DDI mask */ #define ADLS_DPCLKA_DDIK_SEL_MASK … #define ADLS_DPCLKA_DDIJ_SEL_MASK … #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) … /* ICL PLL */ #define _DPLL0_ENABLE … #define _DPLL1_ENABLE … #define _ADLS_DPLL2_ENABLE … #define _ADLS_DPLL3_ENABLE … #define PLL_ENABLE … #define PLL_LOCK … #define PLL_POWER_ENABLE … #define PLL_POWER_STATE … #define ICL_DPLL_ENABLE(pll) … #define _DG2_PLL3_ENABLE … #define DG2_PLL_ENABLE(pll) … #define TBT_PLL_ENABLE … #define _MG_PLL1_ENABLE … #define _MG_PLL2_ENABLE … #define _MG_PLL3_ENABLE … #define _MG_PLL4_ENABLE … /* Bits are the same as _DPLL0_ENABLE */ #define MG_PLL_ENABLE(tc_port) … /* DG1 PLL */ #define DG1_DPLL_ENABLE(pll) … /* ADL-P Type C PLL */ #define PORTTC1_PLL_ENABLE … #define PORTTC2_PLL_ENABLE … #define ADLP_PORTTC_PLL_ENABLE(tc_port) … #define _ICL_DPLL0_CFGCR0 … #define _ICL_DPLL1_CFGCR0 … #define ICL_DPLL_CFGCR0(pll) … #define DPLL_CFGCR0_HDMI_MODE … #define DPLL_CFGCR0_SSC_ENABLE … #define DPLL_CFGCR0_SSC_ENABLE_ICL … #define DPLL_CFGCR0_LINK_RATE_MASK … #define DPLL_CFGCR0_LINK_RATE_2700 … #define DPLL_CFGCR0_LINK_RATE_1350 … #define DPLL_CFGCR0_LINK_RATE_810 … #define DPLL_CFGCR0_LINK_RATE_1620 … #define DPLL_CFGCR0_LINK_RATE_1080 … #define DPLL_CFGCR0_LINK_RATE_2160 … #define DPLL_CFGCR0_LINK_RATE_3240 … #define DPLL_CFGCR0_LINK_RATE_4050 … #define DPLL_CFGCR0_DCO_FRACTION_MASK … #define DPLL_CFGCR0_DCO_FRACTION_SHIFT … #define DPLL_CFGCR0_DCO_FRACTION(x) … #define DPLL_CFGCR0_DCO_INTEGER_MASK … #define _ICL_DPLL0_CFGCR1 … #define _ICL_DPLL1_CFGCR1 … #define ICL_DPLL_CFGCR1(pll) … #define DPLL_CFGCR1_QDIV_RATIO_MASK … #define DPLL_CFGCR1_QDIV_RATIO_SHIFT … #define DPLL_CFGCR1_QDIV_RATIO(x) … #define DPLL_CFGCR1_QDIV_MODE_SHIFT … #define DPLL_CFGCR1_QDIV_MODE(x) … #define DPLL_CFGCR1_KDIV_MASK … #define DPLL_CFGCR1_KDIV_SHIFT … #define DPLL_CFGCR1_KDIV(x) … #define DPLL_CFGCR1_KDIV_1 … #define DPLL_CFGCR1_KDIV_2 … #define DPLL_CFGCR1_KDIV_3 … #define DPLL_CFGCR1_PDIV_MASK … #define DPLL_CFGCR1_PDIV_SHIFT … #define DPLL_CFGCR1_PDIV(x) … #define DPLL_CFGCR1_PDIV_2 … #define DPLL_CFGCR1_PDIV_3 … #define DPLL_CFGCR1_PDIV_5 … #define DPLL_CFGCR1_PDIV_7 … #define DPLL_CFGCR1_CENTRAL_FREQ … #define DPLL_CFGCR1_CENTRAL_FREQ_8400 … #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL … #define _TGL_DPLL0_CFGCR0 … #define _TGL_DPLL1_CFGCR0 … #define _TGL_TBTPLL_CFGCR0 … #define TGL_DPLL_CFGCR0(pll) … #define RKL_DPLL_CFGCR0(pll) … #define _TGL_DPLL0_DIV0 … #define _TGL_DPLL1_DIV0 … #define TGL_DPLL0_DIV0(pll) … #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK … #define TGL_DPLL0_DIV0_AFC_STARTUP(val) … #define _TGL_DPLL0_CFGCR1 … #define _TGL_DPLL1_CFGCR1 … #define _TGL_TBTPLL_CFGCR1 … #define TGL_DPLL_CFGCR1(pll) … #define RKL_DPLL_CFGCR1(pll) … #define _DG1_DPLL2_CFGCR0 … #define _DG1_DPLL3_CFGCR0 … #define DG1_DPLL_CFGCR0(pll) … #define _DG1_DPLL2_CFGCR1 … #define _DG1_DPLL3_CFGCR1 … #define DG1_DPLL_CFGCR1(pll) … /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ #define _ADLS_DPLL4_CFGCR0 … #define _ADLS_DPLL3_CFGCR0 … #define ADLS_DPLL_CFGCR0(pll) … #define _ADLS_DPLL4_CFGCR1 … #define _ADLS_DPLL3_CFGCR1 … #define ADLS_DPLL_CFGCR1(pll) … /* BXT display engine PLL */ #define BXT_DE_PLL_CTL … #define BXT_DE_PLL_RATIO(x) … #define BXT_DE_PLL_RATIO_MASK … #define BXT_DE_PLL_ENABLE … #define BXT_DE_PLL_PLL_ENABLE … #define BXT_DE_PLL_LOCK … #define BXT_DE_PLL_FREQ_REQ … #define BXT_DE_PLL_FREQ_REQ_ACK … #define ICL_CDCLK_PLL_RATIO(x) … #define ICL_CDCLK_PLL_RATIO_MASK … /* GEN9 DC */ #define DC_STATE_EN … #define DC_STATE_DISABLE … #define DC_STATE_EN_DC3CO … #define DC_STATE_DC3CO_STATUS … #define HOLD_PHY_CLKREQ_PG1_LATCH … #define HOLD_PHY_PG1_LATCH … #define DC_STATE_EN_UPTO_DC5 … #define DC_STATE_EN_DC9 … #define DC_STATE_EN_UPTO_DC6 … #define DC_STATE_EN_UPTO_DC5_DC6_MASK … #define DC_STATE_DEBUG … #define DC_STATE_DEBUG_MASK_CORES … #define DC_STATE_DEBUG_MASK_MEMORY_UP … #define D_COMP_BDW … /* Pipe WM_LINETIME - watermark line time */ #define _WM_LINETIME_A … #define _WM_LINETIME_B … #define WM_LINETIME(pipe) … #define HSW_LINETIME_MASK … #define HSW_LINETIME(x) … #define HSW_IPS_LINETIME_MASK … #define HSW_IPS_LINETIME(x) … /* SFUSE_STRAP */ #define SFUSE_STRAP … #define SFUSE_STRAP_FUSE_LOCK … #define SFUSE_STRAP_RAW_FREQUENCY … #define SFUSE_STRAP_DISPLAY_DISABLED … #define SFUSE_STRAP_CRT_DISABLED … #define SFUSE_STRAP_DDIF_DETECTED … #define SFUSE_STRAP_DDIB_DETECTED … #define SFUSE_STRAP_DDIC_DETECTED … #define SFUSE_STRAP_DDID_DETECTED … #define WM_MISC … #define WM_MISC_DATA_PARTITION_5_6 … #define WM_DBG … #define WM_DBG_DISALLOW_MULTIPLE_LP … #define WM_DBG_DISALLOW_MAXFIFO … #define WM_DBG_DISALLOW_SPRITE … /* Gen4+ Timestamp and Pipe Frame time stamp registers */ #define GEN4_TIMESTAMP … #define ILK_TIMESTAMP_HI … #define IVB_TIMESTAMP_CTR … #define GEN9_TIMESTAMP_OVERRIDE … #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT … #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK … #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT … #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK … /* g4x+, except vlv/chv! */ #define _PIPE_FRMTMSTMP_A … #define _PIPE_FRMTMSTMP_B … #define PIPE_FRMTMSTMP(pipe) … /* g4x+, except vlv/chv! */ #define _PIPE_FLIPTMSTMP_A … #define _PIPE_FLIPTMSTMP_B … #define PIPE_FLIPTMSTMP(pipe) … /* tgl+ */ #define _PIPE_FLIPDONETMSTMP_A … #define _PIPE_FLIPDONETMSTMP_B … #define PIPE_FLIPDONETIMSTMP(pipe) … #define _VLV_PIPE_MSA_MISC_A … #define VLV_PIPE_MSA_MISC(pipe) … #define VLV_MSA_MISC1_HW_ENABLE … #define VLV_MSA_MISC1_SW_S3D_MASK … #define GGC … #define GMS_MASK … #define GGMS_MASK … #define GEN6_GSMBASE … #define GEN6_DSMBASE … #define GEN6_BDSM_MASK … #define GEN11_BDSM_MASK … #define XEHP_CLOCK_GATE_DIS … #define SGSI_SIDECLK_DIS … #define SGGI_DIS … #define SGR_DIS … #define _ICL_PHY_MISC_A … #define _ICL_PHY_MISC_B … #define _DG2_PHY_MISC_TC1 … #define ICL_PHY_MISC(port) … #define DG2_PHY_MISC(port) … #define ICL_PHY_MISC_MUX_DDID … #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN … #define DG2_PHY_DP_TX_ACK_MASK … #define PORT_TX_DFLEXDPSP(fia) … #define MODULAR_FIA_MASK … #define TC_LIVE_STATE_TBT(idx) … #define TC_LIVE_STATE_TC(idx) … #define DP_LANE_ASSIGNMENT_SHIFT(idx) … #define DP_LANE_ASSIGNMENT_MASK(idx) … #define DP_LANE_ASSIGNMENT(idx, x) … #define PORT_TX_DFLEXDPPMS(fia) … #define DP_PHY_MODE_STATUS_COMPLETED(idx) … #define PORT_TX_DFLEXDPCSSS(fia) … #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) … #define PORT_TX_DFLEXPA1(fia) … #define DP_PIN_ASSIGNMENT_SHIFT(idx) … #define DP_PIN_ASSIGNMENT_MASK(idx) … #define DP_PIN_ASSIGNMENT(idx, x) … #define _TCSS_DDI_STATUS_1 … #define _TCSS_DDI_STATUS_2 … #define TCSS_DDI_STATUS(tc) … #define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK … #define TCSS_DDI_STATUS_READY … #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT … #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT … #define PRIMARY_SPI_TRIGGER … #define PRIMARY_SPI_ADDRESS … #define PRIMARY_SPI_REGIONID … #define SPI_STATIC_REGIONS … #define OPTIONROM_SPI_REGIONID_MASK … #define OROM_OFFSET … #define OROM_OFFSET_MASK … #define CLKREQ_POLICY … #define CLKREQ_POLICY_MEM_UP_OVRD … #define CLKGATE_DIS_MISC … #define CLKGATE_DIS_MISC_DMASC_GATING_DIS … #define _MTL_CLKGATE_DIS_TRANS_A … #define _MTL_CLKGATE_DIS_TRANS_B … #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) … #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS … #define MTL_MEM_SS_INFO_GLOBAL … #define MTL_N_OF_ENABLED_QGV_POINTS_MASK … #define MTL_N_OF_POPULATED_CH_MASK … #define MTL_DDR_TYPE_MASK … #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET … #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) … #define MTL_TRCD_MASK … #define MTL_TRP_MASK … #define MTL_DCLK_MASK … #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) … #define MTL_TRAS_MASK … #define MTL_TRDPRE_MASK … #define MTL_MEDIA_GSI_BASE … #endif /* _I915_REG_H_ */
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