/* SPDX-License-Identifier: MIT */ /* * Copyright © 2019 Intel Corporation */ #ifndef __INTEL_DE_H__ #define __INTEL_DE_H__ #include "i915_drv.h" #include "i915_trace.h" #include "intel_uncore.h" static inline struct intel_uncore *__to_uncore(struct intel_display *display) { … } static inline u32 __intel_de_read(struct intel_display *display, i915_reg_t reg) { … } #define intel_de_read(p,...) … static inline u8 __intel_de_read8(struct intel_display *display, i915_reg_t reg) { … } #define intel_de_read8(p,...) … static inline u64 __intel_de_read64_2x32(struct intel_display *display, i915_reg_t lower_reg, i915_reg_t upper_reg) { … } #define intel_de_read64_2x32(p,...) … static inline void __intel_de_posting_read(struct intel_display *display, i915_reg_t reg) { … } #define intel_de_posting_read(p,...) … static inline void __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) { … } #define intel_de_write(p,...) … static inline u32 ____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) { … } #define __intel_de_rmw_nowl(p,...) … static inline u32 __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) { … } #define intel_de_rmw(p,...) … static inline int ____intel_de_wait_for_register_nowl(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) { … } #define __intel_de_wait_for_register_nowl(p,...) … static inline int __intel_de_wait(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) { … } #define intel_de_wait(p,...) … static inline int __intel_de_wait_fw(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) { … } #define intel_de_wait_fw(p,...) … static inline int __intel_de_wait_custom(struct intel_display *display, i915_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value) { … } #define intel_de_wait_custom(p,...) … static inline int __intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, u32 mask, unsigned int timeout) { … } #define intel_de_wait_for_set(p,...) … static inline int __intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg, u32 mask, unsigned int timeout) { … } #define intel_de_wait_for_clear(p,...) … /* * Unlocked mmio-accessors, think carefully before using these. * * Certain architectures will die if the same cacheline is concurrently accessed * by different clients (e.g. on Ivybridge). Access to registers should * therefore generally be serialised, by either the dev_priv->uncore.lock or * a more localised lock guarding all access to that bank of registers. */ static inline u32 __intel_de_read_fw(struct intel_display *display, i915_reg_t reg) { … } #define intel_de_read_fw(p,...) … static inline void __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) { … } #define intel_de_write_fw(p,...) … static inline u32 __intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) { … } #define intel_de_read_notrace(p,...) … static inline void __intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val) { … } #define intel_de_write_notrace(p,...) … #endif /* __INTEL_DE_H__ */
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